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Domain: isscc.org

Stories and comments across the archive that link to isscc.org.

Comments · 5

  1. Re:monopoly by Agripa · · Score: 1 · on Intel Finds Moore's Law's Next Step At 10 Nanometers (ieee.org)

    The important criteria is the cost per transistor which must decrease to make the next fabrication node economical. This comes even at the cost of reduced performance.

    2016 Plenary Session 1 - Moore’s Law: A Path Forward

  2. Sweeeeet! by overshoot · · Score: 1 · on IBM's New Processors To Exceed 5Ghz
    I think I know how they're doing the clocking -- they presented on that at ISSCC two years ago.

    There should be some really interesting stuff this year on how they kept the power down.

    Of course, a chip nearly 2 cm on a side is going to be a beast no matter what. This is going to be fun!

  3. Re:Well, this could use some more reiteration... by hattig · · Score: 4, Informative · on A Look Into The Cell Architecture
    We will find out a whole lot more within the next fortnight, Cell is being described in a lot of details at ISSCC 2005 in early February.

    Paper Details:

    • The Design and Implementation of a First-Generation CELL Processor (10.2)
    • A Streaming Processing Unit for a CELL Processor (7.4)
    • A 4.8GHz Fully Pipelined Embedded SRAM in the Streaming Processor of a CELL Processor (26.7)
    • A Double-Precision Multiplier with Fine-Grained Clock-Gating Support for a First-Generation CELL Processor (20.3)
    • Clocking and Circuit Design for a Parallel I/O on a First-Generation CELL Processor (28.9)
  4. Intel may also push new memory standard by morcheeba · · Score: 4, Interesting · on Intel 64-bit Announcements at IDF

    EE Times is also reporting that Intel may be pushing a new kind of RAM interface to compete with existing DDR and RDRAM. At 2 Gbit/sec per wire, this is about twice the speed of current RDRAM and four times the speed of DDR SDRAM. But, more interestingly, this is a point-to-point architecture - unlike the traditional bus architecture, when you add more memory modules you can get more bandwidth. Also notable is that simultaneous bi-directional communications happens over a single wire. Infineon and Samsung have made test chips, and results are to be released at the International Solid State Circuits Conference today.

    I wonder how this figures into their processor/chipset roadmap...

  5. IBM multi-threaded CPU, circa 1998. by Angelwrath · · Score: 1 · on Emergence of SMT

    IBM demonstrated a multi-threaded POWER CPU destined for their AS/400 series of workstations and servers at the ISSCC conference back in 1998. The synopsis of their presentation is available here, as paper 15.3.

    To my knowledge, this chip is either now in use, or very close to being put in an AS/400 or i Series box.