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Currawong writes "eWeek reports that IBM Microelectronics is working with Apple on a 64-bit PowerPC processor called the GigaProcessor Ultralite (GPUL). Unlike previous reports, eWeek now reports that Apple is testing the chip for use with future hardware. IBM apparently also plans to use the processor in linux-based servers. It's believed IBM will disclose some details of the processor in October at the upcoming Microprocessor Forum in San Jose, California. While this story is similar to recent stories about Apple using Power4-based IBM chips in future Macs, the GPUL, unlike the Power4, is smaller, runs cooler and consumes far less power, making it suitable for desktop machines and small servers. The processor is described as having the same 8-way superscalar design fully supporting Symmetric MultiProcessing." We had a previous story about these new chips.

prostoalex writes "ExtremeTech runs a story about IBM planning to introduce a new 64-bit PowerPC architecture for desktops in October at the Microprocessor Forum. The conference agenda tells us that "this processor is an 8-way superscalar design that fully supports Symmetric MultiProcessing. The processor is further enhanced by a vector processing unit implementing over 160 specialized vector instructions and implements a system interface capable of up to 6.4GB/s"." There's also a News.com story.

jpatters tells us that Micro Processor Report is reporting (via MacInTouch) that a russian company (Elbrus International) claims to have a CPU design that achieves 135 SPECint95 and 350 SPECfp95. This compairs to Merced's scores of 45 and 70 respectively. It is claimed to run in a 0.18 micron process at 1.2Ghz consuming only 35 watts and 126 square millimeters of silicon. It includes a 256 Kbyte of on-chip L2 cache. It should also be both x86 and IA-64 compatible. Elbrus 2000 seems to exist (look at what Shevtsov is working on now), and seems to have had some history. Here is Shevtsov's FPU patent. S : I've tried to verify this story, but can't find the copy of MPR -- anybody else have it? Anyone care to speculate how it was done? Assynchronous logic? 256Kb L2 seems rather low though unless they're using a special point-to-point bus. From an Anonymous Contributor

"I get MPR. I've got about 7 minutes before I have to catch a bus, but, from the MPR issue itself:

The processor uses EPIC. The Elbrus team has been together for 40 years, originally designing supercomputers for the Soviet defense establishments. "They've developed computers based on superscalar, shared-memory multiprocessing and EPIC techniques long before papers on those subjects appeared in the West". MPR claims that the lack of a good semiconductor Fab has been what was holding them back. MPR says that the claims would be unbelievable except for the credibility of the team.

The X86 and IA64 compatibility rely on binary compilation assisted by emulation hooks, similar to what Transmeta is apparantly doing. Supposedly Dave Ditzel spent several years while at Sun working with the Elbrus team.

The processor exists only as an executable Verilog database. However, the E2K design is based on the Elbrus-3 processor that was fabricated in 1991. The Elbrus-3 was built in an "ancient process", used 15 million transistors in about 3000 LSI and MSI chips, and delivered twice the performance of a Cray Y-MP."

Some more he sent later:

" It is actually quite a long article... 6 pages plus the cover, I'm about two thirds through it. The architecture is in fact pretty stunning, and very similar to the Merced and the SPARC in several ways. It has a 64K, 4-way instruction cache: one i-cache only. It has two identical, synchronously-loaded 8K L1 data caches, and a 256K, 2-way, 4-bank L2 data cache. In addition, it has a 4K array pre-fetch buffer for use in loop overlapping. There are two regions, each with an L1 data cache, a 256-entry register file, and three ALUs. The regions are symmetric except that only one region has a divide function.

A great deal in this processor is left to the compiler, a fact that is demonstrated by the single, 64K i-cache; this will only work if the compiler does its job. Much also depends on the compiler's ability to identify instructions that can be executed in parallel. With an optimal instruction load, the multi-ported caches can provide a potential operand bandwidth of 288 Gbytes/sec at a processor clock of 1.2GHz. Much effort is expended to avoid branching; extensive branch prediction support is provided, and in some cases it will actually just go ahead and execute both sides of a branch to avoid doing the branch at all; with so many parallel execution paths, the cost of doing so is much lower than what would be the cost of branching.

When loops are identified, an effort is made to overlap the loop execution, taking advantage the same mechanism as used for the sliding register windows. The 4K FIFO Array prefetch buffer helps to feed data to the overlapped loop. In loop mode, for perfectly optimal code, the processor can rates as high as 23 operations per cycle.

Much of the processor is designed in standard static CMOS gates, but some of the critical paths through the processor use self-reset gates, which do not have a clock but rather are triggered by the completion of cycles in previous gates. According to MPR, these are estimated by Elbrus to run 10-15% faster than static CMOS gates.

Just a couple more facts about Elbrus: The Elbrus-1 computer was a "...superscaler, RISC, processor with out-of-order execution, speculative execution, and register renaming..." This machine was designed and built... between 1973 and 1979!! They dumped superscaler designs becuase they were too complex for the payoff. The Elbrus-3, built between 1985 and 1991, used "an EPIC-based VILW CPU", implemented as a "16-processor shared memory system"

They started working on the E2K in 1994, and it is now at Verilog RTL stage, with compilers and binary-compilation software written. MPR expresses great doubt that a home will ever be found to build the processor, what with the Russian economy as bad as it is, and most capable semiconductor houses already in the midst of implementing their own designs or just not wanting to compete with Intel."

MPR's analysis of Katmai is that it offers no benefits for business users or consumers not interested in 3D or video. In fact, Willamette should be shipping by now (4 years since the P6 was designed), but it hasn't even taped out... suggesting the proliferation of P6 cores (Klamath, Deschutes, Mendocino, Dixon, and Katmai) and the development of Merced is spreading Intel's engineers too thin.

This year's Microprocessor Forum looks like it's going to be rather interesting. Two new x86 vendors will be presenting their latest work: Rise and Transmeta. Rise is attacking the x86 market with low power designs, somewhat like IDT did with Centaur, (although their efforts appear to be waining). Transmeta will be presenting a RISC chip that can read x86 instructions.

The Microprocessor Report is carrying an editorial discussing Whitney, Intel's upcoming Northbridge with integrated graphics: too little too late. Already the i740 had a short life, to satisfy gamers needs in 2001 Whitney will have to integrate something more powerful -- but that's not what Intel appears to be planning.

The Microprocessor Report is carrying an editorial discussing Whitney, Intel's upcoming Northbridge with integrated graphics: too little too late. Already the i740 had a short life, to satisfy gamers needs in 2001 Whitney will have to integrate something more powerful -- but that's not what Intel appears to be planning.

In a move confirming the reasons it purchased Metaflow, SGS-Thomson has announced that it will be cloning Slot 1. This will be SGS's first recent x86 chip not based on a Cyrix designed CPU. In a similar deal to IBM's, SGS has had the option of manufacturing Cyrix processors under its own brand name to give Cyrix Fab capacity. However it did not exercise this option. Metaflow is interesting in that it pioneered out of order execution and uses other novel techniques. While SGS does not intend to sell its chips on the open market, it does increase the competition in the x86 market.