Oracle Demos New SPARC T4 Processor

MojoKid writes "Oracle is publicly demonstrating its new T4 processor today and is shipping beta test systems to selected partners. The new T4 chip is a major departure from previous designs. The T4 offers a maximum of eight cores per physical chip and keeps the T3's eight-threads-per-core limitation. The T4 compensates for its lower maximum theoretical throughput in several ways. First, the T4 is an out-of-order processor with an enhanced branch predictor. Its maximum speed is said to be at least 3GHz, nearly double that of the 1.67GHz T3. Oracle claims the chip's single-threaded performance has been significantly boosted, and expects T4 to deliver a 2x-7x speed increase in single-threaded workloads compared to T3."

Comments

Single thread performance

[toQDuj]

"Oracle claims the chip's single-threaded performance has been significantly boosted"
Be that as it may, the TX chips were designed to handle a vast multitude of threads with lower performance per thread. So now they are trying to turn that design around? Seems to me they are designing the processor equivalent of the half-track.

Re:Single thread performance

[lanc]

Well, it is still 64 threads per socket, or 256 threads per box that that run parallelly. Is that not vast enough? With the 5x signlethread performance compared to the T3?

Re:Single thread performance

[Anonymous Coward]

Whatever benefits Oracle DB the most.

Re:Single thread performance

[Anonymous Coward]

Ridiculous. It's as if Intel started to design for low power, or ARM for high performance.

Seems like the industry is marching towards unification of design goals. Having the best product for part of the market is no longer interesting, you must be a player in "whatever everybody is doing these days".

Re:Single thread performance

[MetalliQaZ]

This comment may have been meant as a bite at Oracle, but it is really a good point. The T4 may be a departure, but that doesn't mean it isn't warranted. The chip is still massively parallel, but it has obviously been refocused. The question is, what does the application need? Perhaps the engineers saw the biggest gains for DB applications in boosting single thread performance. MySQL probably will benefit from the same things that benefit Oracle DB. What are the customer demands for power consumption? Are the tradeoffs balanced? Perhaps lower-power chips require too many servers to store and cool. The T4 still looks like a mighty processor.

Still, if they venture too far into Intel's Xeon space, they will have a hard fight indeed.
-d

Re:Single thread performance

[spiffmastercow]

Well, it is still 64 threads per socket, or 256 threads per box that that run parallelly. Is that not vast enough? With the 5x signlethread performance compared to the T3?

It may be "vast" enough, but given that 4-8 cores is the most that will typically get used, it may not be *fast* enough, and may be a big waste.

Re:Single thread performance

[V!NCENT]

A lot of CPUs in one CPU with low power consumption sounds nice, but that sounds a lot like a GPU setup to me.

Given that GPGPUs are taking over, I smell that they are in need for another problem. My guess is that this powerhouse is seriously going to kick Intel in the balls with Intels failing demonstrations of realtime raytracing.

So where can I get my hands on a Sparc workstation? >:-)

Re:Single thread performance

[Vectormatic]

If you are only using 4-8 cores at a time, you are clearly not the target audience for these chips.

Re:Single thread performance

[FreakyGreenLeaky]

but given that 4-8 cores is the most that will typically get used

You clearly don't understand the target market of these chips. In fact, your statement is hilariously ignorant.

Re:Single thread performance

[owlstead]

This is very much a generic CPU, nothing to do with vector processing. It's main tarket is enterprise & communication application servers. Hence the crypto-units and networking capabilities build in. A GPU might well outrun it regarding vector processing though.

Re:Single thread performance

[Anonymous Coward]

Actually, they may be - by definition, when a single thread (one out of 8) gets boosted to the high performance mode, it's one per core - so up to 8 *single threaded* applications could be boosted to high performance. Doing this with a single socket is very cool, being able to do this on a per-core basis is even cooler.

given some software company's inability to write efficient multi-threaded code, it gives as close as you can get to the best of both worlds. Some cores doing high perf single thread, others doing many threads per core (java code, etc).

Re:Single thread performance

[Anonymous Coward]

These are full-power cores, though, not the ultra-simplified stuff you see in GPUs. It's designed for extremely high-load systems - heavily-used web servers, for instance. It's actually a very interesting design - each "core" is a sort of barrel processor. Every clock, it runs the next thread. If it's blocked, waiting for memory access, it just goes to the next one. With that many threads, it's effectively never running NOPs because it's waiting on memory, so that 1.67gHz is a lot more efficient than an equivalent x86, POWER or Itanium. It also doesn't need nearly as much cache - the T3 had only 6MB of L2 cache, compared to 30MB of L3 cache on Xeon E7s (on top of 2MB of total L2 cache).
Unfortunately, it's not a workstation chip at all. I'm checking Oracle's website, and every single one of those servers is "price by request". But when they're selling a 600GB hard drive for it for over a grand, I think it's safe to say that you're more likely to see a workstation based on ARM than based on that.

Re:Single thread performance

[Anonymous Coward]

Ridiculous. It's as if Intel started to design for low power, or ARM for high performance.

Am I really the only one who remembers that ARM 2/3 originally did outperform Intel 80386/i486 vastly? In the late 1980s, when x86 was just over 1 MIPS, ARM was at 8 MIPS.

Re:Single thread performance

[segedunum]

The point that the OP was making was that the target market for these chips is terribly small. The big market is for ever bigger single tasks and threads to be completed in less and less time. The fact that they've had to come up with this halfway-house tells you that this is unlikely to save SPARC as a platform.

Re:Single thread performance

[Anonymous Coward]

Yes, you are. I'll get off your lawn now, mister.

Re:Single thread performance

[TheRaven64]

Unless you happen to have a massively parallel application that needs to serve a huge number of concurrent users. Like, say, a database. Or a web app.

Re:Single thread performance

[Anonymous Coward]

Terribly small? Most any business who currently uses SPARC would be a target market for these systems. If you consider that small, then I guess we have different opinions on the definition.

The T4 merges the strengths of the T-Series and M-Series together. Looks good to me.

Re:Single thread performance

[ThePhilips]

Am I missing something?

Has Sun produced any non-Tn CPU after UltraSPARC IV+ in 2005?

I haven't heard anything about UltraSPARC V - only the T line.

P.S. But probably I shouldn't care anymore. My company recently has just changed the "strategic platform" from Solaris 10 to RHL6.

Re:Single thread performance

[Anonymous Coward]

It's not been refocused per-se, it's more that it's been made even more multi-purpose.

Let's say you load up a T4 based box with several containers (Solaris 10 para-virtualization - think enhanced chroot'd jails), one or two for database, a couple for web services, and a couple for file transfer services. Each of these containers will share resources as defined by the administrator who set the box up. Single thread hungry apps like the database will perform well, while the multi-thread apps like the web services will also thrive.

Re:Single thread performance

[spiffmastercow]

Unless you happen to have a massively parallel application that needs to serve a huge number of concurrent users. Like, say, a database. Or a web app.

In almost any relational database your bottleneck is going to be storage -- you might be able to process things 32 times as fast, but you're still going to have to wait for that save op to complete before doing anything else. As for web apps, well.. it depends.

Re:Single thread performance

[Bengie]

The T3 has a shared FPU among all those cores. The FP performance is horrible, but it can crank out the int performance required for an efficient web/db server.

Don't expect Ray Tracing with an INT heavy CPU.

Re:Single thread performance

[Bengie]

A heavy read database, like a news site, will have nearly everything cached in memory.

I've done ad-hoc aggregate functions against non-indexed tables with over 100mil rows, and they return in sub 10ms times. Cached table data can be fast.

Re:Single thread performance

[afidel]

The more interesting question is will 256 threads per box be enough to compete with 160 threads per box from Intel (8x 10 core Xeon's with hyperthreading) or the monster boxes from IBM, or heck even the 512 thread M9000 they get from Fujitsu.

Re:Single thread performance

[swordgeek]

Short answer, no. Not really. There is no UltraSPARC V. The 'traditional' SPARC architecture lives on in the M-series, which has SPARC64 CPUs by Fujitsu.

We are jumping from Solaris to RHEL as well. It's possible that we work for the same Canadian ISP, but it's more likely that our companies have made the same decision as dozens of others.

Re:Single thread performance

[mcclungsr]

The T1 had a single FPU shared among 8 cores.. The T3 (and T2) has an FPU per core.

Still, your point about ray-tracing is probably valid, compared to other processors available. If I had a heavily threaded application, I would definitely want to look at T-series SPARCs.

Re:Single thread performance

[maraist]

The problem is that hyperthreading CPUs and x64-64 EPIC are predicated around floating point performance. The idea is that if you're FPU bound, then you want to minimize RAM latency by flipping between threads while you have FPU-load stalls.. You add speculative execution, predicate registers, pipeline execution stacks to minimize branch-misses, etc. But it's all about FPU with 200 clock execution times (e.g. divides and transcendental ops - as with FFT).

But I'm sorry, no matter how fast you make their FPUs, they're not going to beat FPGA or ASIC or raw-silicone GPU's. These bastards optimize memory paths and reduce critical path latencies.. The only advantage CPUs have over GPUs is that you can context switch unrelated tasks better than with GPUs.

A vast majority of apps in the world are NOT FPU based. They are pure integer. And moreover, these days, they are RAM constrained.. If your're writing a NoSQL DB procedure to perform zlib or merge-sorting or state-machine syntax parsing, FPU oriented architectures are of ZERO benefit. This is all RAM -> branch-prediction related. That is, read-data, make a decision, jump to new code (which triggers new RAM loads) run two or three instructions, then repeat. While SOME of the app state-tables and code-paths can get cached efficiently, the input stream is generally far larger than your L3 cache (on the order of gigabytes).

So, SOME of the memory pre-loading, branch-prediction, and on-stalled-thread-ctx-switch could be leveraged.. But MT apps suffer from barriers in critical regions.. Namely if you memory stall while holding a lock, you cripple the parallel performance.

Co-processes are very efficient (e.g. apache pre-fork, postgres co-threads with specific shared-mem-segments, erlang, ruby-unicorn, etc) in that they organize very small messages to pass between processes and keep all remaining cache-lines isolated to their single thread and thus semi-dedicated CPUs. This can very nicely leverage co-processors without necessarily saturating RAM -though if the apps themselves are RAM-bound you still have problems; BUT if you have NUMA, the CPU can segment memory spaces better with co-processes than with MT. That being said, the SUN light-weight-threads are (I believe) designed around shared memory-spaces having minimal context-switching time v.s. posix-threads or normal co-processes, so they can't really take advantage of co-processes as well as MT.. So SUN light-threads are forced to endure potentially bad programming by DB, file-IO, OS, signal-processing applications.. Namely if you can't create isolated memory regions (malloc/free-locks, IO/pipe-locks, concurrent-data-structure 'critical-region' locks, etc), you'll find yourself dirtying shared cache-lines so often, you actually find yourself running slower than if you were just single-threaded.

I know, for example, a simple merge-sort can run significantly slower (3x) when run in parallel v.s. single-threaded predominantly because of intel's MESI implementation. Well, not necessarily 3x slower human-time wise, but in consumed CPU time with little or no visible decrease in human-response-time.

As another example, mysql INNODB had a inverse performance curve for the longest time.. Meaning, the more physical CPUs you added, the SLOWER it's total throughput would be.. Predominantly due to excessive critical-region locks. Many of those locks have been replaced with less-accurate atomic spin-locks (as with sequence-counters). Namely you can now 'lose' a primary key's sequential value under the right circumstances - but at the benifit of removing a major classic stall-point. But INNODB is still full of complex algorithms that require critical-regions. Lock-free-code is really hard and is very limiting. But that isn't to say people haven't figured out how to architect good designs. 'redis' NoSQL and erlang based apps (like rabbit-MQ) are good examples.. Namely copy-on-write small data-structures.

But there are two types of apps that have lots of parallel threads. Those with MASSIVE memory requirements and those that

Oh...

[neokushan]

Well that's nice. Good for Oracle.

Re:Oh...

[Anonymous Coward]

Good for us, too. The more competition the better. And that machine seems competitive. Welcome back from the dead, Sparc!

high end CPUs from the database company

[Anonymous Coward]

err... OK. Guess they gotta parse those SQL statements.

Re:high end CPUs from the database company

[NoNonAlphaCharsHere]

Well, in fairness, they did add an evil bit(TM) to the flags register. Unfortunately, in Oracle's case, "jump on evil" is an unconditional branch.

Re:high end CPUs from the database company

[ThePhilips]

No no. You should familiriaze yourself with Oracle DB.

The CPUs are busy colliding on SQL statement cache global lock.

Re:high end CPUs from the database company

[DoctorPepper]

I wish I had mod points, that made me laugh! :D

Time machines work in reverse?

[said213]

“The spread of civilisation may be likened to a fire; First, a feeble sparc, next a flickering flame, then a mighty blaze, ever increasing in speed and power.” - Nikola Tesla

Single threaded. Teh Futar has arrived.

Not the point of SPARC

[Anonymous Coward]

Is it me, or did Oracle completely miss the point of SPARC? We used to use SPARCs where I work for huge, multi-thread or child-spawning applications. If you want a number cruncher, go somewhere else. Go buy a POWER CPU. SPARC's shining glory is the massively threaded model where you spawn tons of little instances of the same thing that serve a quick, non-intensive purpose and die. Once again, Oracle is taking something they bought and trying to ram the square object into the round hole they call their business model.

Interestingly enough, the captcha for this was "idiots"

Re:Not the point of SPARC

[Anonymous Coward]

Meanwhile, a big purpose of database code is acquiring MUTEX locks. Having lots of cores running spinlocks doesn't make a lot of sense for them.

Re:Not the point of SPARC

[TheLink]

Is there a way for a CPU to make mutex handling easier and more efficient?

Another thing which might be worth looking into speeding up is "gettimeofday" and "trigger on event or register/memory=certain value" - I bet there's lots of code which regularly checks "is it time to do X yet?" or "wait till X happens" (e.g. wait for connection or data).

Maybe these aren't that CPU intensive so speeding them up won't help much in performance?

Re:Not the point of SPARC

[eclectus]

Is it me, or did Oracle completely miss the point of SPARC? We used to use SPARCs where I work for huge, multi-thread or child-spawning applications. If you want a number cruncher, go somewhere else. Go buy a POWER CPU. SPARC's shining glory is the massively threaded model where you spawn tons of little instances of the same thing that serve a quick, non-intensive purpose and die. Once again, Oracle is taking something they bought and trying to ram the square object into the round hole they call their business model.

Interestingly enough, the captcha for this was "idiots"

Do you really think Oracle could turn the ENTIRE chip engineering boat around in a year and a half? This best-of-both-worlds fast single threaded and massively multithreaded design was probably in the works for YEARS before Sun was bought.

Re:Not the point of SPARC

[laffer1]

gettimeofday calls are a problem for several applications. Postgres and MySQL both had to do some changes to lower the number of times they were called to speed up performance. The problem is that open source software is often designed for Linux. gettimeofday is cheap on Linux because they chose to use a less precise timer than other operating systems. I'm not certain how fast it is in Solaris, but I doubt it's a speed demon. This is a software problem though. The best solution is to update a shared memory segment with the value periodically and just read that from libc. It's a pain to implement though.

I think the argument the GP was making was that less cores means less contention for the lock. Combine that with a faster chip and it is faster. They would need to rewrite large portions of the database to get away from needing mutex. There are other locking strategies as well as ways to write structures that can be read all the time. Some databases are designed to be lock free like couchdb. The problem there is that it's NOSQL and assumes you want to version things and never delete.

Databases are usually lock intensive and many try to do row level locks rather than table locks now.

Intel added instructions to the CPU that can be used for implementing locking primitives that are much faster. I think they're called CAS http://en.wikipedia.org/wiki/Compare-and-swap

Re:Not the point of SPARC

[davecb]

Linux is not unusual in seeing developers call gettimeofday/gethrtime with wild abandon, thus slowing the programs they're trying to measure the time of (;-)) For this reason, Solaris time calls are register/location reads, and ethe code sequences are so short that they fit into the the syscall dispatch table. Therefor the caller never really enters the OS at all to get the time.

The interesting new work on locks is "transactional memory", and there's a series of articles about it and Linux memory in general at LWN. See Memory part 8: Future technologies by Ulrich Drepper. The hardware they describe as the testbeds are SPARCs.

--dave

Re:Not the point of SPARC

[jmitchel!jmitchel.co]

The direction of the T4 has been set for some time. It's overdue - the single thread performance on the T series is basically miserable and has barely improved since the original T chips. My job involves doing a lot of single thread activities on T series hardware, and that makes me a sad panda.

Re:Not the point of SPARC

[hattig]

This chip was probably designed before Oracle finished the takeover of Sun, so saying that Oracle is making this change is quite a leap.

Also the linked article suggests why the design decisions were made in this chip - namely extreme threading compared to the mass market CPUs is getting more and more niche as the mass market CPUs get to 16 threads per socket themselves. Hence this chip going down a higher performance per thread model, with a mode for running a single thread very fast on a core should it need it.

And ultimately you still have the OS scheduler if you want to run more threads than the hardware can handle, and given that the per-thread hardware performance is far higher on this CPU you're not giving up much, if any, threading capability compared to the previous generation.

Re:Not the point of SPARC

[ThePhilips]

Is there a way for a CPU to make mutex handling easier and more efficient?

No. It is inherently expensive operation because the updates to critical section must be propagated between all the CPUs/cores (and their caches). CPU ops for mutex itself are puny, compared to the (invisible) mechanics beneath which guarantees the cache coherency. (More CPUs/cores you have - higher the potential overhead.)

Another thing which might be worth looking into speeding up is "gettimeofday" and "trigger on event or register/memory=certain value" - I bet there's lots of code which regularly checks "is it time to do X yet?" or "wait till X happens" (e.g. wait for connection or data).

`gettimeofday` is already optimized and not a real syscall on Linux and Solaris.

Maybe these aren't that CPU intensive so speeding them up won't help much in performance?

They are CPU intensive - but negligible - because they were already heavily optimized.

Overall, GP's suggestion that DB take lots of locks is sort of right - but misses the fact that there are many many locks so collisions are relatively rare. Those are most of the time logical data locks, not real mutexes. And collision are most of the time also of the logical nature: one user tries to update data which are currently being updated by another; one use tried to read data which were updated but not committed by the other; and so on.

DB are generally IO bound: they must provide guarantee that committed data were safely written to disk. This is where the most of DB's performance is wasted - waiting for the disk to do its job.

Re:Not the point of SPARC

[julesh]

Is there a way for a CPU to make mutex handling easier and more efficient?

No. Modern CPUs already support waiting for a spinlock without actually using any execution units (which on a highly-parallel CPU like the Tx processors means the time that would be spent executing them can be allocated to another thread) or any memory bandwidth (by monitoring the cache/memory bus for alterations rather than actively polling). Solaris (and I believe other OSs) will quietly decide whether to use a spinlock or a queue-based system for a mutex lock operation depending on whether the thread that holds it is currently running. Essentially, this is about as efficient as you can get (the queue based system involves a user->kernel->user context switch, but as that's a hotpoint for optimisation for many different scenarios anyway, we can assume that that's already about as good as the CPU designers can get it as well).

Re:Not the point of SPARC

[TheLink]

Speaking of slowing the programs, I notice a lot of programs use delays in the order of seconds.

While this might be fine for human facing/usage scenarios, for other scenarios isn't 1 second a very long time for a CPU?

Would delays of 1 millisecond or less be better? Or is there some problem with that? IIRC FreeBSD had some HZ thing, and by default it was 100Hz, so 1 millisecond might be a prob :).

Re:Not the point of SPARC

[tlhIngan]

Is there a way for a CPU to make mutex handling easier and more efficient?

No. Because mutexes as slow (though highly efficient already).

Most architectures of today provide all the necessary tools to implement lockless algorithms which are more complex, but faster. They're less efficient (because they often do a "try and get lucky" style of processing), but if you have a ton of threads and pretty idle CPUs, it's less of an issue.

And support for this comes in the form of memory barriers (read and write - they're different) and conditional exchange instructions (if value of memory is same as register X, then swap X and memory) up to native word size (or more). The latter is important as you need to be able to swap pointer-sized things atomically.

An example of "try and get lucky" is in singleton object initialization. Say your code instantiates an object, and the object needs ot initialize.

If the object has been instantiated before, you return the existing object. If not, you instantiate and initialize. So far, exactly as how it's done normally, except no lock was taken during the check (!).

Now you initailize the object, and the magic happens near the end. You do a memory barrier to ensure all I/O and memory accesses are done. You then do an atomic compare-and-swap with the memory to hold your instance. If no one else has initialized it yet, it should still be NULL, so you compare with NULL and exchange with your instantiation.

If you succeed, you get the old value of the memory (i.e., NULL). If you fail, you get your instance pointer back (because the exchange failed). If you succeeded, object is initialized. If you failed, someone else initialized it under you, and you destroy the object you initialized and use the one already there.

You can extend this for processing as well - often by using a sequence counter to "flag" what has been done. Or linked lists (being able to verify no one stomped over your next pointer). Or many other structures.

it's less efficient because you're doing more work than necessary (e.g., if you have 100 threads, all 100 may initialize the singleton simultaneously, but only one will succeed and you would throw away the results of the other 99).

Re:Not the point of SPARC

[maraist]

"Is there a way for a CPU to make mutex handling easier and more efficient?"
mutex's are VERY efficient with cache-oriented MESI and MOESI instructions, the problem is what you do while another thread owns the mutex. You can either spin-loop or context-switch to another thread. Specifically if thread A locks then has several cache-misses, then thread B would have to spin for thousands of clock-ticks. When you have 80 CPUs that might not be too bad (though it burns power), but if you have 2 CPUs, then that's likely highly wasteful.

"trigger on event or register/memory=certain value"
I believe intel provides a block-until cache-line-updated instruction. I believe that's how Linux futuex and OS-level schedulers work if IIRC.

"I bet there's lots of code which regularly checks "is it time to do X yet?" or "wait till X happens" (e.g. wait for connection or data)."

Well, wait-for-connection is an OS thing. If you use epoll, IO-Completion, kpoll, or even ancient unix 'select' you transfer the overhead of IO to the OS which is very event-driven (and thus doesn't necessarily have a lot of blocking structures). Namely ethernet frame-driver running on CPU-3 can in theory directly transfer to thread-16 after completion which is blocking on a TCP packet when the OS determines it's received enough data to be awoken.

As for 'is it time to do X yet' isn't as bad as you might think (well, I don't have that much imperical evidence, but I've worked in this space).
Instead of 'polling', you can leverage a priority-queue, such that if there is literally nothing critical-to-run, you quickly test the head of the queue for it's execution time-stamp. Then do a time-of-day operation (all while in the OS, so no additional context switching). If a < b you flag the blocking thread for execution (possibly transfering directly to it). Here the slowdown comes when you add/remove an item from the temporal priority-queue (namely O(log(n))). So this is a function of how many temporal waits are scheduled/completed, but is independent of how long it's supposed to wait.. When there is literally no work to perform at all (all CPUs are about to go idle), then you look at your priority-queue and ask how long before the next scheduled event.. Then you can make a CPU go to sleep for that long (using interrupt controllers if need be).
Generally you're going to wake up 32 times a second anyway, and the marginal overhead of re-testing a time against the priority-heap-head 32 times a second is nominal (I can run 800,000 java-based time-of-day calls per second.. plenty of room for those 32).

To boot, the OS doesn't need to know about all the scheduled tasks. It only needs to know about one per thread at most (generally only about 0 .. 3 at any given time, with a few socket-timeout type apps bringing it into the hundreds). Apps can, for example implement their own timer logic that mimics this priority-queue model (java does, for example).. Thus one thread can be OS-bound on a timer that is the nearest temporal event in a pool of potentially thousands of scheduled events (e.g. a Java Timer or memory-based Quartz).

What I see the greatest problem with are peer-CPU's modifying common cache lines..

Namely if you have a job-queue data-structure where N threads are pulling/pushing out-of/on-to, then you have a single spot in memory that EVERY thread must modify in order to transfer work.. This is a massive bottleneck.. One that ironically you don't have in single CPU configurations. This is something that I think CPUs can work to address. Especially as co-process and message-passing systems become more prevelant (erlang type languages or message-queue NoSQL models).

One reason Intel CPUs suffer from this is that when two CPUs concurrently modify a cache-line, everybody is forced to 'flush' their cache line and re-read from RAM.. This not only makes those accesses no faster than main RAM, it's competing with everything else you want to do with RAM - increasing latancy massiv

Re:Not the point of SPARC

[maraist]

"DB are generally IO bound: they must provide guarantee that committed data were safely written to disk. This is where the most of DB's performance is wasted - waiting for the disk to do its job.".
Sometimes. When they are IO bound, then yes, locks are of trivial importance. But DBs generally also serve as massive coherent caches and lock-managers. And those caching operations are VERY susceptible to critical-region code. Namely MySQL INNODB had an inverse performance characteristic with the number of CPUs for a long while. Further, recently, it was shown that by skipping the SQL layer of MySQL-INNODB and using simple direct HTTP calls into the storage layer, performance was improved measureably.

There's no accounting for bad code (which is most likely the case with MySQL optimizations), but I definitely feel that the programming world is solely inadequately prepared for multi-threaded programming.

Basically we need to focus on lock-free algorithms (or wait-free, or read-lock-free as appropriate). They should focus on optimisitic locks instead of pessimistic locks. Use compare-and-set operations/spin-loops. Use stack / context-variables instead of globals, etc. But most people just think in their 1960s sequential style and go; oh, two guys touch this so let me throw in a mutex. Then you find when you double the CPU count (or even machine count) that the system degrades miserably.

Re:Not the point of SPARC

[maraist]

"Essentially, this is about as efficient as you can get"
I don't know about that. alpha/AMD added the 'mesh' CPU network, where you talked to routed neighbors for memory/BUS access, and thus not every CPU needs to spin it's transistors on cache operations. I don't know how advanced that got, but there's no reason that N,S,E,W cache controller nodes can't determine the scope of dissemination of cache-reads, and thereby localize snoop and lock-cache-line calls. Compre-and-set can be implemented IN the cache-line. You've got an address-line and a data-line. Why not add a cas bit on the routed bus and say 'Here's the old data, and it's address, and set the cas bit; then on the next clock, the data line will contain the new data. The mem-controler reponds with a read-complete operation or invalid'. You already have comparison logic for the address lines in their fully-associative cache logic; no reason you can't implement CAS there too.

So now you completely avoid a BUS-lock.. The cache atomicly (within a cache-clock-tick) owns the data.

I'm not a fan of mutex-spin-locks, because most algorithms that are fast enough to warrent a context-switch-free operation generally can use an optimistic-locking algorithm. Thus, I believe OS ctx switches or CPU-oriented thread-swap operations are field (e.g. some type of yield operation). But there are integer or pair-of-integer algorithms that can make heavy use of such CAS operations. And generally, the first step of a mutex is such a CAS.

If you were crazy enough to want to use semaphores instead of mutex's (hopefully because you actually want a constrained resource count, and not because you just prefer semaphores), then this CPU operation wouldn't make sense.. I doubt you want a full-on adder in the cache-controller (though I suppose that's possible too). Namely instead of 'lock; xadd [m1], 1'. You'd have "st_add [m1], 1" where the cache-controller is required to implement read, add, re-write (atomicly) instead of having the CPU do it.

Next is the furthered notion of topological CPU configurations.. Namely, pin thread-5 to CPU-2 then pin thread-6 t CPU-3 (which is adjacent), and the OS tells both CPUs that a shared memory segment (including mutex regions) is ONLY available to those two CPUs. And thus you can pass synchronous control signals between them.. Again, special instructions are required.. But now you can use 'barrier' instructions.. Similar to an idle spin loop (wait until barrier signal arrives from co-processor indicating the pipeline of work has new data. But this now starts competing with GPUs and CELL processors.

I'm sure there are other possible operations, such as direct register to remote-CPU register transfer operations.. Similar in principle to the SUN SPARC register window, you can have an in/out suite of registers where instead of function-call communication, we're facilitating asynchronous co-processors pipeline communication operations.

There are code paths that make sense to implement these sort of pipeline co-process architectures. Any place a 'spawn task' operation happens, that can be optimized in assembly + OS as a co-process pair. You would need some specialized C function APIs:

Future f = DispatchTask(data_structure); // co-process/ co-thread dispatch ....
mytype result = f.get(); // co-process barrier (CPU might context switch to peer thread)

Oracle?

[aglider]

Oracle is as deep in CPU technology as Berlusconi is deep in reliability.
Maybe it'd read "SUN, an Oracle acquisition, will demo a new T4 Sparc CPU".

Does that make any sense?

[aglider]

I mean, to (re)introduce a new CPU in the market?
Either the T4 can run Oracle SQL in silicon or it won't fit in between the Intel/AMD mature technology on one side and the rising (and power saving) ARM on the other one.
Yes, you can build an "Oracle appliance" with whatever CPU you want, even your very own design. But then will the market share justify the efforts in CPU design?

No, I don't think they won't ever succeed.

Re:Does that make any sense?

[EthanV2]

No, I don't think they won't ever succeed.

Sooo... You think that they will succeed?

Re:Does that make any sense?

[Kjella]

Either the T4 can run Oracle SQL in silicon or it won't fit in between the Intel/AMD mature technology on one side and the rising (and power saving) ARM on the other one.

If you think the T4 is even remotely in the same market as ARM you're only showing your own ignorance. They're more in league with IBM's POWER7 and Intel's high end Xeons, running massive servers.

Re:Does that make any sense?

[angel'o'sphere]

# prstat
Total: 341 processes, 9909 lwps, load averages: 20.86, 19.36, 20.41

# prtdiag -v
System Configuration: Sun Microsystems sun4u SPARC Enterprise M9000 Server
System clock frequency: 960 MHz
Memory size: 262144 Megabytes

Only roughly 3 processes per core ... and yes that is 262 GIGA BYTES of Ram. How much again can an ARM address?

Well, keep in mind: when we talk about SPARC or the Power PC architecture we also talk about memory bandwidth, failover safety, attached I/O devices etc.

I don't see anyone trying to build "big iron" with ARMs right now.

Re:Does that make any sense?

[davecb]

You don't run the sql in silicon to speed things up, you worry about the speed of joins in main memory.

--dave

Re:Does that make any sense?

[aglider]

NO, they won't. Typpo!

Re:Does that make any sense?

[aglider]

I do am ignorant. But I think I know the difference, technical and comemrcial, between Intel, AMD, ARM, POWER7, Alpha and so on.
I simply say, there's no room in the market for another CPU, as almost all of the "atlernative" ones already failed.

Re:Does that make any sense?

[aglider]

Correct.
Do you why none (else) is building "big iron" like that?
Probabily because too few people is asking for them.
The market buzzwords are "cluster" and "clud". Not "big iron".
I don't mean that real 64bit hardware is not good. I meat it hardly will succeed.
You know the glorious story of the wonderful Motorola 68K and 88K. Beautiful CPUs, stinky business.

Re:Does that make any sense?

[aglider]

Yeah! That's the RDBMS duty! Which is software.
So what'd the be the plus of yet another RISC CPU?
With super-pipelined Intels and AMDs behaving almost like RISC, with multimegabyte L3 caches and so on, the gap between RISC and CISC is almost zero.
Apart of the power hunger.
Mine was humor, anyway. A CPU running SQL in silicon is an absurdity.

Re:Does that make any sense?

[Anonymous Coward]

processes != threads.

Re:Does that make any sense?

[the linux geek]

Nobody else is making big iron? IBM, HP, Fujitsu, Unisys, Hitachi, NEC, and Groupe Bull are just irrelevant?

Re:Does that make any sense?

[Anonymous Coward]

My mother was a fujitsu you insensitive clud.

Re:Does that make any sense?

[Anonymous Coward]

Ah, double negatives. How can't you not love them?

Re:Does that make any sense?

[joshuac]

Memory size: 262144 Megabytes
Only roughly 3 processes per core ... and yes that is 262 GIGA BYTES of Ram. How much again can an ARM address?

Just a minor detail, that looks more like 256 "GIGA BYTES".

Re:Does that make any sense?

[Anonymous Coward]

SPARC is not a new architecture. You might not have come across it, but that is a different issue entirely. The T4 is the latest in a long line of SPARC CPUs, and enterprise level customers have been incredibly happy with them.

I am not aware of any CPU which runs SQL statements natively; that would be quite an achievement, but the architecture would have to be very complex to allow for execution of non-SQL code (such as a kernel) on a more traditional instruction set. That would be an architecture that would be very difficult to introduce into the market!

Re:Does that make any sense?

[Anonymous Coward]

Oh noes, did you call Seagate too?

"Manufacturers are stealing 24 bytes from every kilobyte!" Say it ain't so!

Re:Does that make any sense?

[Anonymous Coward]

It's a server chip. The massive threading they've got right, and it's great for that, but servers aren't just about running oodles of servlets - although that's a huge part of it. The T4 will doubtless outperform any Intel competitor at the same number of simultaneous threads because Sun has that part of the internals down just right and Intel does not.

The absolutely fastest arrangement Intel has is 4-way SMP, 6-way internal cores, 12 threads per core. (4x6x12) And I do not believe Intel has done any serious work on SMP in a very long time, so the 4-way may no longer be possible. So 72 threads is you're most likely limit, 288 threads is the absolute limit Intel could hope to deliver if they provide an SMP chipset capable of supporting the latest i7 CPUs.

With the T4, you're limited to a 16-way SMP, 8 internal cores and 8 threads, giving you a 16x8x8 arrangement. That's 1024 simultaneous threads across the entire arrangement.

Sure, you could build an Intel cluster that matches or beats a T4 system, but the less tightly-coupled your system is, the slower the internal communication and the more complex the message navigation becomes, so although it would beat the T4 on raw power, most of that raw power is unusable due to latency.

Re:Does that make any sense?

[blue_teeth]

Amen to this.

For the basement types x86 desktop guys. While the whimpering noise you make, please visit a Enterprise Class Datacenter of a large organization (if you are allowed inside). An hour downtime of their Operations System would result in couple of million dollar (USD) costs. This is where Sparc and Power PCs run.

Please do not compare your Suzukis with a McLaren F1's. (Its a theoretical argument).

Yes, I have migrated large enterprise Operations Systems from Sparc to x86_64 (Opteron).

Re:Does that make any sense?

[Darinbob]

This is not a new CPU trying to squeeze in, this is an upgrade to a CPU that is already in the market!

And if society kept saying "we already have one of those, thank you very much" we'd never make any progress at all.

Re:Does that make any sense?

[Anonymous Coward]

Actually it's 262 giga bytes, or 256 gibi bytes. http://en.wikipedia.org/wiki/Orders_of_magnitude_(data)

Re:Does that make any sense?

[djdanlib]

Huh, I am required to have multiple-factor ID access to one of my large global enterprise's datacenters in case the primary admins get hit by a bus or something, and those systems are all running on modern x86 hardware. Most of what you refer to is running on Microsoft OSes, virtualized under Microsoft or VMware servers on Intel hardware. Sure, some of it is Linux, but it's still on x86. The only remaining Sparc servers are being phased out and no longer perform critical functions. They've been replaced with lower-cost, redundant x86 equipment. I also participate in certain user groups, and my peers there are doing similar things with their large global enterprises. We're not even at the forefront of this movement, so anyone behind us has to be a really slow mover. Perhaps yours just hasn't migrated yet, for whatever reason...?

This new processor isn't even available to use yet, so all we can do is speculate about what it'll do to our efficiency. I look forward to ANY technology that can leave the current state of affairs in the dust, so I'm all for this processor being great.

I'd be a little more careful about making sweeping generalizations and calling people names. :)

Re:Does that make any sense?

[cthulhu11]

... not to mention the freedom from BIOS and anachronistic video consoles

Re:Does that make any sense?

[Anonymous Coward]

no, they think that:
"I don't think that they will never succeed"

In other words that they MIGHT succeed at some unknown time in an unknown future of an unknown universe, the key is the "will" (being the positive of "won't) which puts the sense of the sentence into a modal future (yes I know what I just did and that it is considered controversial, but the mangling of the parents English is one situation that helps to justify this understanding since it is the only possible understanding of the sentence)

That modal future is hypothetical and means that the actual utility of the sentence is only as a worthless and empty statement of vaporous nothingness. In short, he said nothing at all in 7 words, not even a record number of words for saying nothing. Any two-bit Texas governor can do that without breaking a sweat.

Re:Does that make any sense?

[maraist]

I am suspicious of such numbers. You need to pick an application and run it on two machines for comparison. Number of active threads is independent of the number of CPUs - and while this means overhead in context switching into and out-of CPUs, if the reason they're stalled is memory throughput or disk IO, then CPU context switching is irrelevant.. And guess what, the memory throughput has little to do with the CPU.. Namely you can construct a NUMA motherboard where each CPU has localized RAM (and thus unaffected by threads in other zones).

The main reason I call BS on 2, 4 or 16 threads per core is that this explicitly only allows a single actively running thread; it merely means that IF you can do NON RAM work in the other 15 threads, then when thread-1 stalls you can get useful work done by quickly switching without OS interaction. But that's a big IF.

Re:Does that make any sense?

[Anonymous Coward]

Memory size: 262144 Megabytes
Only roughly 3 processes per core ... and yes that is 262 GIGA BYTES of Ram. How much again can an ARM address?

Just a minor detail, that looks more like 256 "GIGA BYTES".

No, that would be 256 gibibytes. It's 262.144 gigabytes.

price?

[dutchwhizzman]

Will it be able to compete with HP and Dell servers in price this time? 8 core intels cost less than 10K these days, I hope SUN^wOracle will start understanding competitive pricing for a change.

Re:price?

[backslashdot]

According to the article, apparently they make up for that by charging extra if you want to run Oracle database on an x86 CPU.

Re:price?

[eclectus]

remember, 8 cores, 8 threads per core, multiple chips per system. I'm sure it's able to be LDOM'ed out as well, so you could in theory have up to 256 single-threaded seperate servers running in this one box. Not in the same league as a little dell/HP box. Like someone else said, This is going after IBM P7. Or people who really want to consolidate.

Re:price?

[Anonymous Coward]

8-core intels isn't the same market segment, while a single-socket (8 cores, 64 threads) may or may not compete on price/perf (it comes down to what the perf difference is between 16 intel threads and 64 T4 threads), a fully decked (4-socket, 32-core, 256 threads) traditionally beats out it's throughput equivalent x86 counterpart on price/perf by a wide margin, and it always beats out the equivalent x86 cluster (fewer nodes -> less memory and disk overall, which adds up to a lot more than the rest of the hardware, especially on larger scale DBMS applications where you're pushing tables out into memory).

But hey, if all you need is 8 cores and 16 threads, it doesn;t make much sense to buy a 64 core and 256 thread system, unless you know you'll need to scale to that kind of throughput, it'll cost less and offer better perf (interconnects ftl) to keep adding in T4s as you need them, than to add nodes to a cluster (again, memory, storage, etc) the initial cost is higher, but the long term cost of expansion is much lower.

Keep in mind also, that if you're running Oracle EE, the per-socket licensing cost significantly less of a 1-4 socket T4 server, whereas it will kill you on the throughput equivalent x86 installation. (and before anyone rags on Oracle for the per-socket licensing, RHEL does that, too). There's also one of the main reasons Oracle acquired Sun in the first place (to be able to provide the entire stack top to bottom from a single vendor, like IBM does) to consider, if you buy your hardware from a vendor, if they offer the option, you'd be more inclined to equire the rest of your stack from them too, you're already saving on Oracle EE, but you're also saving a bundle on the OS, Oracle offers both Solaris and Oracle Linux for a flat rate of $2499 per machine, which gets you all of one socket from Red Hat, plus you save on support.

People are a little baffled at why Oracle didn't opt to double the core count or thread count as the Niagara line of processors has in the past, but it's because Sparc is still the most paralell CPU of its class CoolThreads kills Hyperthreading and doubles Power and Itanium in that regard, what hurt the Niagara processors was that while there were more threads to work with, the threads were slow enough that Xeons would win out on occasion by having few, but faster (by a factor of two) threads than the 1.6ghz Niagaras, now the threads are nearly twice as fast as before, and that's four times as many as on a Xeon, which brings it level with the Power CPUs (which have up to nearly twice the clock, but half the threads)

Re:price?

[TheSunborn]

A shame that the benchmarks show that any decent x86 dual-processor box Hp or Dell will beat this box in both price and performance. (But not in power usage)

The thing I don't understand is: If you have code which are multit-hreaded enough to max out a T3, then the T4 will not give you any performance benefit. This is odd, considering how old the T3 is.

Re:price?

[Bengie]

Great for servers, bad for clusters. Very power efficient, but very picky on the type of work they do. Very expensive, but worth it if you need high densities.
Semi-niche market.

Re:price?

[Anonymous Coward]

I would love to lose 256 machines all at the same time. That is something my boss would say. "Just buy 1 really big box and put everything on it. Think of the money we could save in infrastructure costs." I stand in amazement at times that he is a director. damn...

Re:price?

[Anonymous Coward]

nice touch.

Price?

[Anonymous Coward]

Does anyone know the price range of a 1 to 2 CPU server for the new T4 chip?

But -

[Anonymous Coward]

Will it run Linux?

Re:But -

[xmorg]

No, but it runs FreeBSD

Re:But -

[Anonymous Coward]

Why would you want to run a kiddie O.S.? Linux is total crap.

Re:But -

[unixisc]

Sparc runs several Linux distros, such as RHEL, Debian, and also the 3 major BSD ones - OpenBSD, NetBSD and FreeBSD. I see no reason why T4 shouldn't. What I do wonder is - does Oracle offer Oracle Linux as an option on Sparc h/w?

Re:But -

[Anonymous Coward]

SPARC is officially supported by the Linux kernel, but it's not a mainstream platform. Red Hat does not produce a SPARC version of RHEL.

Nobody (well, maybe a few people with specialized goals/needs) goes out to buy an expensive SPARC box to run Linux on. There is for all practical purposes zero consumer interest in that combination.

The only commercialized SPARC Linux distro I can think of is Wind River; Wind River is popular with the embedded/telecom space where Linux has an edge in features (and Sun/Oracle has an edge in NEBS-compliant hardware, i.e. Netra SPARC servers)

Otherwise... If you're buying SPARC gear, you're going to want to run Solaris on that. It's optimized for the hardware Sun/Oracle sells, tested on the same hardware, and frankly, it's a superior OS.

Re:But -

[Anonymous Coward]

Ho ho ho. Why would you want to run Slowaris on the thing? The anaemic cores are already slow enough as it is, I wouldn't have thought you'd want to make them even slower.

http://www.stdlib.net/~colmmacc/2006/04/13/more-ubuntu-on-t2000/

Amusing.

[Anonymous Coward]

I always find it so amusing to see the same people that are always raving about how great it is to have AMD competing against Intel, how everything needs to be ported to ARM for competition, saying "SPARC should go away and we should just stick to Intel". Huh? Do you want competition or not?

Pricing? No, *licensing*

[Brandon Hume]

It's all very nice that they've decided to try and up the single-thread performance. However, it's worth noting that the only thing worthwhile to run on a SPARC nowadays (thanks to Oracle's PMITA licensing structure) is Oracle DB. You buy an Oracle box to run Oracle. Any other workload is nonsensical, as you'll get better single-thread performance from x86, and you'll get way more cycles per dollar from... well, just about any other hardware/OS combination out there.

So as you consider purchasing this higher-clocked box, I've been told that the Oracle licensing for this machine will be 0.5 per core, while the T3 is 0.25 per core. Basically Oracle will cost approximately twice as much per core on this machine. I'm not a DBA... does that make any sense, when databases are traditionally I/O-bound?

Incidentally, my first paragraph caused me pain to type... I'm my organization's SPARC and Solaris expert, and I was a big pusher of the platform. Oracle's takeover and subsequent psychotic support costs and absolute blindness to any workload not DB-oriented was a fair kick in the pants to me. I'll fully admit that I'm not impartial.

They've made Itanium!

[Anonymous Coward]

Itanium worked out well enough for Intel. Good luck with your version Oracle!

Re:Pricing? No, *licensing*

[angel'o'sphere]

Basically Oracle will cost approximately twice as much per core on this machine. I'm not a DBA... does that make any sense, when databases are traditionally I/O-bound?

The matter with traditions is that they are outdated at some point. DBs are no longer I/O-bound since typical querries return gigabytes of results that need to be joined and ordered. At least in our days universities have research projects running to utilize the CPU better in modern DBs.

Cores?

[Bigbutt]

Considering the licenses are for the number of cores, changing the number of cores from 16, or 32, or 256 to 8 cores would certainly bring the Oracle DB license costs down again. And since that's the reason we haven't been upgrading our Sun systems and have been moving to Dell R710's or HP, there might be some strategy involved from Sun (since this couldn't have been something that took a bit over a years to produce).

[John]

Re:Pricing? No, *licensing*

[Bigbutt]

I'm with you and am a big supporter of Solaris and Sun but the Oracle licensing costs were killing the company and killing me since I couldn't get new Sun boxes to replace the old gear. Hence the move to Dell and HP and the transition to mysql for the database side (although when Oracle bought Sun, it threw a bit of a wrench into the works).

[John]

yo dawg

[decora]

i heard you like threads, so i put a CPU in your CPU so you could give all your money to Larry Ellsion while you give all your money to Larry Ellison!

Re:yo dawg

[V!NCENT]

I saw a T4 blade version with 300GB costing around 600 euro's and a terminal costing around 100 euro's, so I figured that a rack/workstation could add up to just around a 1000 dollars. But according to the replies, this is probably impossible to get (1) and worthless for anything that doesn't float (2).

Sadly...

Re:yo dawg

[V!NCENT]

Correction: Worthless for floating point.

I'm not dead yet

[mevets]

Really, I'm feeling quite a bit better.

It would be nice to see sun rise again; although masters of their own demise, they have suffered the way Brittany did.

Sparc runs Linux too

[unixisc]

But won't RHL6 run on Sparcs as well, like current RHEL 5 does? Such a change shouldn't prevent them from continuing to use their old Sparcservers. Of course, if they're moving away from Oracle, they may not care to buy any T4 based systems - at least not from Oracle.

Re:Sparc runs Linux too

[Anonymous Coward]

Redhat dropped SPARC ages ago. Any EL5 SPARC build you might have seen was built by a third party and isn't supported by Redhat.

Re:Sparc runs Linux too

[ThePhilips]

I was under impression that HP offered us a sweet deal on x64 servers (ProLiants) our management couldn't refuse. And why on earth run a Linux on proprietary hardware?

Old SPARCs would remain of course, but only for purposes of support and maintenance of old versions of our software.

We have bunch of old T2 - and they ... suck. Even on highly multithreaded Java workloads.

Re:Sparc runs Linux too

[tqk]

Redhat dropped SPARC ages ago.

Fine. Slackware for Sparc

Re:Sparc runs Linux too

[swordgeek]

Actually, you can pretty much blame that on Java - it's a disaster on highly parallel gear. (We got Sun to eventually admit that, after a disastrous aborted rollout of Directory Server on T series machines.)

Still - The T machines are very much a niche market, and that niche is disappearing quickly. I suspect there will never be a T5 processor with any significant changes.

Good luck with the ProLiants. They ain't what they used to be, according to a friend recently ex- of HP.

Re:Sparc runs Linux too

[ThePhilips]

Good luck with the ProLiants. They ain't what they used to be, according to a friend recently ex- of HP.

They are just generic x64 servers, with a decent support contract from HP. I doubt they are worse or better than the cheap generic Intel boxes from any other manufacturer.

Re:Sparc runs Linux too

[WorBlux]

Almost all hardware is proprietary. Perhaps you mean uncommon? Anyways the designs of the T1 and T2 have been publicly released. http://www.opensparc.net/about.html

Re:Sparc runs Linux too

[ThePhilips]

CPU specification != system architecture.

The former is mostly about wiring a CPU. And instruction set.

The latter is about: memory and memory controllers, IO controller, interrupt controllers, external RTCs, and the rest of carp you usually find soldered on a motherboard. All the carp for which the OS requires a proper driver.

While CPU spec might be free, the rest of the controllers, which are required to bring up the system, are mostly proprietary H/W.

Re:Sparc runs Linux too

[swordgeek]

Fair enough. It's just that up until about three years ago, the Proliants were solid and beautiful tanks, which were almost on par with the new Sun gear at the time.

Re:Sparc runs Linux too

[segin]

No, the x86 platform is not "proprietary". It may have proprietary extensions (GPU acceleration features, etc.), but there is a universal base set of hardware interfaces and behaviours that every single x86 machine has. And this base set is openly documented, in full, no NDAs required.

Re:Sparc runs Linux too

[dbIII]

These days a whitebox with a SuperMicro board is a lot cheaper with more features at the high end. At the low end I don't know why you would bother looking at HP.
HP stopped moving but the rest of the world didn't.

Re:Sparc runs Linux too

[WorBlux]

That means it's not secret and standard compliant,, not that anyone can go a manufacture x86 processors with the modern instruction sets) without paying licencing fees or having a large patent pool of their own to do cross-licencing with. But this isn't quite true anyways, Intel hasn't released full spec sheets on their chipsets since the Pentium two or three making it really hard to get coreboot running on modern intel boards.

Re:Sparc runs Linux too

[ThePhilips]

These days a whitebox with a SuperMicro board is a lot cheaper with more features at the high end. At the low end I don't know why you would bother looking at HP.
HP stopped moving but the rest of the world didn't.

You missed the bit about "decent support contract." We need our suppliers to be able to provide customers with systems which they can support for 5-10 years. Except for the HP, IBM and Sun/Oracle very few companies are doing it.

Re:Sparc runs Linux too

[dbIII]

Ok, missed that, mostly because in my part of the world support contracts are crap and typically involve some teenager fresh out of a tech course flying in the day after you need them to attempt to perform some task they do not understand and have never done before. I bought a couple of spare IBM tape drives and autoloaders for less than their yearly support cost after one such incident.
Dell of course are several times worse. HP don't really do much support near me.
I got stuff from Racksaver/Verari for a while but they changed their on site support policy to return to base on the other side of the fucking world (and then the courier put a forklift tine through the server on the way back). "Decent support" depends entirely on who is employed doing it in your local area, and if you don't know it's worth finding out before you get stung.

Re:Sparc runs Linux too

[Pieroxy]

Actually, you can pretty much blame that on Java - it's a disaster on highly parallel gear.

Do you have references for that? In my experience, Java handles threads mostly well. The last experience I have was on a 16CPU Sun beast (don't remember the model unfortunately). Is that a deficiency of Java on this architecture?

Re:Sparc runs Linux too

[Anonymous Coward]

Well, a Sun SPARC is not really more proprietary than an Intel x86. The instruction set is actually more open, but both actual microarchitecture of the CPU and IO chipsets are of course proprietary to the company. System programming docs are released for both, and Linux supports Sun's systems very well (up to T3, at least, not sure about T4).

Linux actually has been known to run on T3 faster than Solaris, so that's one reason. Another is that it's an open source and more portable OS.

Re:Sparc runs Linux too

[swordgeek]

The advantage of dealing with a big name comes of being a big player with a big support contract.
Our division within the company runs about 1800 unix servers right now. That doesn't include the switches, the storage, workstations, etc. etc.. That kind of clout gives us traction when we call for support on a system.

If I'm prepared to spend six or seven figures on annual support, then the big companies actually make sense. If I'm looking at a few to a few dozen servers, then no--go with something small, and do your own in-house support.

Re:Pricing? No, *licensing*

[hattig]

So you would prefer that they had 16 of the T3 cores at 0.25x per core? Running at maybe 2GHz each because of the design?

Nah, 8 T4 cores at 0.5x per core, and far greater per-core performance, seems to be a better deal to me. You might lose half of your threads per CPU, but as the article says, that level of threading is getting more and more niche.

But not as good a deal as not using Oracle in the first place.

Re:Pricing? No, *licensing*

[Anonymous Coward]

Why in the world would you move from oracle -> mysql when oracle -> postgresql is so much easier? You can even buy support from a company at a tiny fraction of the cost of oracle that will give you near perfect pl/sql compatibility in postgresql, with support. Oracle is even crippling mysql now, it really makes no sense at all to move to it from an Oracle DB.

Re:Pricing? No, *licensing*

[Anonymous Coward]

> DBs are no longer I/O-bound since typical querries return
> gigabytes of results that need to be joined and ordered.

What?! Either you're incompetent or your place of business is highly atypical, or perhaps both.

Re:Pricing? No, *licensing*

[Bigbutt]

Got me. I'm in operations, not in development.

[John]

Alternative CPU's?

[Anonymous Coward]

Excuse me butwhen was there such alternative CPU's? Intel stole patents and used bribes to shut-down HP's PA-RISC and HP/Compaq's DEC Alpha. Microsoft bribed CEO's of Caldera and Sun to disappear off the face of the earth while slinging lawsuits and FUD at neighboring competitors. SGI similarly had leadership problems that it stagnated, but it's talent all moved independently to Nvidia if not Intel and ATI/AMD.

The two major infiltraitors are the Intel and Microsoft chaingang, both of which have ruined more companies a,d removed product diversity, scalability, and quality. In a world of art in science, Intel and Microsoft are taggers and counterfeiters. They were the alternative that used granted research money to ruin fields of expertise to force customers and competitors to their own propriety. Consumers voted with money too, and now everyone suffers withese two obese Alternatives becoming the main line of only-available products.

Have a nice day, sir.

FAIL AT FIXING IS FAILURE

[Anonymous Coward]

No, it looks exactly like 262 GIGABYTE and 256 GIBIBYTE

Re:FAIL AT FIXING IS FAILURE

[Anonymous Coward]

No, it looks exactly like 262 GIGABYTE and 256 GIBIBYTE

There's no such thing as a gibibyte no matter how much idiots wish for it.

Re: wait periods (was:Not the point of SPARC)

[davecb]

If I want to let other programs make progress, I'll put myself to sleep for human kinds of time periods, like "the rest of the second" for small waits, 1-3 seconds for big ones, and up to 10 if I can signal the human with something like a watch cursor.

--dave

Re:Pricing? No, *licensing*

[Anonymous Coward]

Oh, how I understand you. I am in the same position now.
Support costs and sparc hardware costs are outrageous. And more important - almost any software works on Linux/BSD x86 better and faster, because
HA features also is crappy - crash after crash we are told by a support that we needed firmware level +2 than we had or patch 1254520-19 instead of 1254520-21. Even simple HA features like redundand PSUs has failed for us, and loss of one power source triggered crash of blades chassis along with all servers. 5 year old HP ProLiants continued to work in the same racks I am fed up with all this and I am planning a career change either to Linux or even to windows admin.

Funny

[Anonymous Coward]

Sun leaved competition years ago, while Intel and AMD struggled for the top edge. There's no magic bullet, Oracle is way far behind Intel/AMD/IBM ... The new T4 will be quite expensive, and customers would prefer to stick to either Intel/AMD or IBM Power...
 

Price performance ratio remains the same

[Anonymous Coward]

Well, I realized that price performance of T3 is the almost the same on T4. T3 has 16 cores@1.65Ghz and T4 has 8 cores@2.85Ghz, so oracle has doubled the price per core ratio for 11g on T4 but the licensing prices remains the same.