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Adapteva Announces Epiphany Mesh Processor
MojoKid writes "A new company, Adapteva, has announced its own entry into the field of many core, mesh-connected processors. The company's Epiphany architecture is an array of simple, RISC-based microprocessors. Each processor contains ALU and FPU units, 32K of SRAM cache and each processor node incorporates a router. Nodes communicate with each other via mesh networking. The implementation is capable of scaling up to a 64x64 array (4,096 processors). Adapteva claims that Epiphany is capable of delivering unprecedented performance per watt, with a 16-core array offering up to 19Gflops at 270mW on a 28nm process."
It sounds like something for a specific application:
"Unlike other designs, however, Epiphany is designed to be an FPU co-processor, not an independent chip"
Does it run on my bsd-powered toaster?
http://xkcd.com/619/
Does this mean I should dust off my OCCAM textbooks?
Donte Alistair Anderson Roberts - hi son!
Karma: Chameleon
Tilera has had 64 and 100 cores for a while now.
"Tilera's primary product family is the Tile CPU. Tile is a multicore design, with the cores communicating via a new mesh architecture, called iMesh, intended to scale to hundreds of cores on a single chip. As of September 2010, shipping versions of Tile have 36 or 64 cores. The goal is to provide a high-performance CPU, with good power efficiency, and with greater flexibility than special-purpose processors such as DSPs. In October 2009, they announced a new chip TILE-Gx100 based on 40nm technology that features up to 100 cores at 1.5 GHz. Other Gx family members will include 16, 32 and 64-core variants."
http://en.wikipedia.org/wiki/Tilera
64 Cores
"TILE64 is a multicore processor manufactured by Tilera. It consists of a mesh network of 64 "tiles", where each tile houses a general purpose processor, cache, and a non-blocking router, which the tile uses to communicate with the other tiles on the processor. The short-pipeline, in-order, three-issue cores implement a MIPS-derived VLIW instruction set. Each core has a register file and three functional units: two integer arithmetic logic units and a load-store unit. Each of the cores ("tile") has its own L1 and L2 caches plus an overall virtual L3 cache which is an aggregate of all the L2 caches.[1] A core is able to run a full operating system on its own or multiple cores can be used to run a symmetrical multi-processing operating system. TILE64 has four DDR2 controllers, two 10-gigabit Ethernet interfaces, two four-lane PCIe interfaces, and a "flexible" input/output interface, which can be software-configured to handle a number of protocols. The processor is fabricated using a 90 nm process and runs at speeds of 600 to 900 MHz."
http://en.wikipedia.org/wiki/TILE64
100 Cores
"The TILE-Gx processor family brings 64-bit multicore computing to the next level, enabling a wide range of applications to achieve the highest performance in the market."
http://www.tilera.com/products/processors/TILE-Gx_Family
Tilera processors seem to be less geared towards FP, however. The first generations did not even have FPUs
Green Arrays -- has 144 cores running Forth as their machine code, at about 700 (integer) mips per core, on a 20 dollar, 0.18 micron (180nm) chip. Built by a few guys including Forth inventor Chuck Moore on basically a shoestring budget. Each core has just 64 words of ram (18-bit words) but for some purposes that's all you need. Power consumption is around 0.5W with all 144 cores going and close to zero at idle. That's around 200 GIPS/watt though they're integer mips not floating point.
Sounds like the perfect chip upon which to build a modernized version of the coolest looking computer ever
This is more a GPGPU competitor. Tilera is designed for things like big web apps where you have lots of not particularly computationally strenuous tasks that need handling with relatively low latency. This is designed for the kind task where you want to use a GPU, but your algorithm doesn't fit. It would probably also be good at things like ray tracing.
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It runs Linux which, last time I checked, works for general purpose computing. 100 cores... sweet.
Price or GTFO!
(Im showing my age here!)
Imagine a Beowulf Cluster of these!
(Sorry , it was the voices!)
N ...
Electronic Music Made Using Linux http://soundcloud.com/polyp
Sounds neat, but what caught my attention was the misread "Adapteva Announces METH Processor." Oops, I thought it was going to be one heckuva an article. Still neat, though.
Vote monkeys into Congress. They are cheaper and more trustworthy.
It'd be better if it could scale to a 3 dimensional array of 64x64x64 for 262144 cores. A neural network may actually be able to do something intelligent in a package small enough to use in robotics.
Anyone else remember back when you logged off, you were told how many flops you had used (because you paid for them) ?
I want to delete my account but Slashdot doesn't allow it.
Each processor contains ALU and FPU units, 32K of SRAM cache and each processor node incorporates a router. Nodes communicate with each other via mesh networking. The implementation is capable of scaling up to a 64x64 array (4,096 processors). Adapteva claims that Epiphany is capable of delivering unprecedented performance per watt, with a 16-core array offering up to 19Gflops at 270mW on a 28nm process."
You anti-Apple morons just don't get it. It's not about the specs, it's about the design!
RISC was always good at SMP. Back in the day, that was its biggest draw. If they had a 28nm process it would have been unprecedented news. What is really interesting about this chip, IMHO, is the embedded router. It brings to mind the MPC860.
Having to work for a living is the root of all evil.
I've got one of these on my desk as I write. I've actually been working with it for several months now, and it's pretty sweet. It's intended to be a DSP co-processor coupled to an FPGA. The company I work for (BittWare) has invested heavily in Adapteva, and we are introducing some boards featuring a handful of 16-core Epiphany chips (which we have rebranded as "Anemone") and an Altera Stratix 5 FPGA.
The tools are Linux-only at this point, but that's more than OK by me. I think this is the first time I've ever not been forced to use Windows to develop code for a new processor.
The target application is anything that requires lots of DSP but can't burn many watts.
</shameless plug>
In theory, practice and theory are the same. In practice, they're not.
It will be a complete bitch to program. The native Forth is a tiny subset of standard Forth. There is a more normal higher level Forth that can be run on top of the native one, but this would have a dramatic impact on performance. Each CPU has almost no memory. The code space size per CPU is only 512 instructions. Forth is compact, but that is still a really small amount of code. Any meaningful computation requires that algorithm be distributed across the array. Also, the CPU is implemented in asynchronous logic. Just imaging the opportunities for obscure timing errors. As far as large scale users are concerned, I don't see who would want to use something this non main stream.
Why is Snark Required?
Tilera's chips don't have FPUs, they're therefore no good for most compute intensive applications (e.g. scientific computing, simulations...) We've seen on-chip networks, local scratch pads (read: caches) and FPUs on many previous chips. What sets this design apart is the combination of all three on a large scale. It's really like the IBM Cell BE, just not 1D, but 2D. Interesting.
Computer simulation made easy -- LibGeoDecomp
A while back, Google bought out a research company that was in stealth mode making chips. All we really know is that the founder of the company did a bunch of work in routed microprocessors.
Google has a very strong reason to be interested in work per watt (and area). If searches run much better on custom ARM-ish network-ish chip clusters, we'll never notice. Intel might.
Anyway, their guys though the approach was good enough for an acquisition.
My God, it's Full of Source!
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