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Flexible Circuits By the Slice
MTorrice writes "Researchers have demonstrated a way to make high performance, flexible integrated circuits using almost exclusively standard equipment and materials already needed to make conventional chips. Such a method could allow electronics manufacturers to build new devices, such as smart medical implants and flexible displays, without needing to significantly overhaul current production protocols. The method, developed by researchers at the University of Texas, Austin, started with researchers patterning integrated circuits on silicon wafers using a standard production line. They then cut off the top 20 to 30 micrometers of the wafer using a thin wire—like slicing a block of cheese—to produce a thin, flexible platter of circuits."
You made me think of pizza (this low-carb diet is hard enough as it is!).
You need to be intoxicated somehow to believe that monocrystalline silicon will bend instead of break, even at 10-20um thickness. Moreover, the circuit's behavior will be drastically affected by the mechanical stress.
Overall, research for the sake of wasting time and money and for papers to be published.
Yes, 1-3 mil thinned wafers feel like a piece of plastic, easily flapping around (though, I would not want to literally bend them at 90 or 180 degrees at small radius and expect them to still work). If you ever had a chance to handle a thin microscope cover slip (http://en.wikipedia.org/wiki/Cover_slip), you would know how it feels, especially if you imagine that it is 4-8 inches in diameter -- pretty flexible, monocrystalline, or not.
And, a (seemingly much more reliable) version of the process has been around for years, involves [polishing the backside of the wafer, instead of trying to "slice" through Si with a wire. See http://en.wikipedia.org/wiki/Wafer_backgrinding . By the way, after your wafer is polished down to couple of mil thickness, you can etch vias through it and deposit backside metal, to serve as a groundplane -- not a big deal for CMOS, but pretty big for high-power low-layer-count RF GaAs/InP chips.
Paul B.
>using almost exclusively standard equipment and materials already needed to make conventional chips.
So that will be a small $5,000,000,000 for a state of the art semiconductor factory then.
http://www.tomshardware.com/news/intel-fab42-14nm-cpu-factory,14545.html
I should use this sig to advertise my book ISBN-13 : 978-1501515132.
Yes, most wafers today are back-lapped to 100-200um, almost always at the assembly site (due to the fragility of a 8" or 12" plate only 4-8mil thick).
This article describes how to peel off a 20um thick sheet, which is almost and order of magnitude thinner and uses a much less reliable method (cracking along the Si layers) than back-lapping. Unfortunately, I'm not subscribed to that society to read the article you've linked to (same people, isn't it?).
Also, given how much a bare wafer costs these days compared to the cost of the cracking/slicing (including yield, re-polishing etc), I'm not sure it's even economical to slice a wafer into several slivers.
Sorry, the paper that you are referring to was not posted by me, but by another person in this thread -- and no, I could not read it either.
I do know (from my previous life ;-) ) that, I think, 6" III/V wafers were routinely thinned to 1 or 2 mils (25-50 um), yes, those were not 8-12", but then they were not exactly mass-produced either, and, needing backside vias and backside metal they *had* to be that thin.
And yes, I am skeptical about the yields of that "cracking" process myself, even without invoking reusing the remainder of the wafer for actual fab again, just wanted to point out that thin enough substrate will, indeed, bend, not break (at first! :) )!
Paul B.
Proton-Induced Exfoliation, that is. They both seem to create flexible silicon wafers of a similar thickness. I wonder whether that process would work for already-created circuits, and whether it would be more reliable. I also wonder whether this process is cheaper.
(T>t && O(n)--) == sqrt(666)