Project IceStorm Passes Another Milestone: Building a CPU
beckman101 writes: FPGAs — specialized, high speed chips with large arrays of configurable logic — are usually highly proprietary. Anyone who has used one is familiar with the buggy and node-locked accompanying tools that FPGA manufacturers provide. Project IceStorm aims to change that by reverse-engineering some Lattice FPGAs to produce an open-source toolchain, and today it passed a milestone. The J1 open-source CPU is building under IceStorm, and running on real hardware. The result is a fairly puny microcontroller, but possibly the world's most open one.
I'm pretty sure CPUs are supposed to be closed so as to keep dust out.
It bothers me that most people don't care. They don't understand that Intel/AMD CPUs could or will have backdoors. If not now, then very soon in the future.
Buggy and node-locked tools sure sounds like what I used. Hopefully an open source version can fix the shitty stability along with the shitty vendor lock and pricing.
There are plenty of fully open source CPUs around.
There is a community building CPUs from discrete logic (http://mycpu.selfhost.it/), from transistors (http://www.extremetech.com/computing/128035-how-to-build-an-8-bit-computer-from-scratch) and even from relays (http://www.nablaman.com/relay/).
There are also Forth CPUs which are freely embeddable into a FPGA (the J1: http://www.excamera.com/sphinx/fpga-j1.html) and which can be purchased now (http://excamera.com/sphinx/gameduino/).
According to TFA, the Lattice iCE40 has a very minimalistic architecture with a very regular structure - I don't do FPGA but I am curious to know if the Lattice iCE40 is the only FPGA which has both minimalist architecture and regular structure?
Are there any other FPGA platform which enjoys similar features?
? Program Forth in who want
What is to stop Lattice from simply shutting down this project for an open FPGA toolchain for their FPGAs?
Or does Lattice not care about this particular project for some reason?
What is to stop Lattice from simply shutting down this project for an open FPGA toolchain for their FPGAs?
Why and how would they shutdown this project? This project is the FPGA equivalent of writing a open source assembler or compiler for new CPU. They do not publish their bitstream format, but reverse engineering is perfectly legal.
Jan
Better question, WHY would they want to shut this project down? This is free advertising! It also only works for the one FPGA chip (so far). IMHO, Lattice should welcome this with open arms (when they're not welcoming Open ARMs :)
You are wrong, as its much harder to put backdoors in an regular fpga as into a cpu since you don't know how the slices are used later on.
Actually it's publicity for Lattice which is the third player far behind Xilinx ans Altera (well, Intel now).
It IS free advertising!
It intrigued me so much that I just bought an evaluation board.
The dangers of excessive individualism are nothing compared to the oppressiveness of excessive collectivism
With my limited understanding of what this is, I am kind of surprised that they are not actively helping the project. Any competitors can do this more easily than this group likely can. Their stuff is all covered by patents anyhow. Why not help? It looks good and will improve sales in a niche market where no other competition exists. It seems that they could benefit if they helped and the publicity would be priceless (even if limited in scope). Hell, even Microsoft has folks working in the open source realm. I can not imagine that this is all that different.
"So long and thanks for all the fish."
What is to stop Lattice from simply shutting down this project for an open FPGA toolchain for their FPGAs?
Reverse-engineering for the purposes of interoperability is a protected activity under the DMCA (and basically all other purposes are prohibited.)
"You're right," Fisheye says. "I should have set it on 'whip' or 'chop.'"
With my limited understanding of what this is, I am kind of surprised that they are not actively helping the project.
Basically, hardware companies are, on the whole totally mental. For some reason, they have all their expertise in hardware and produce hardware for a living and then throw a total shitfit over the software and believe that their super special awful crashy piece of shit software is really the important thing and wrap it up in all sorts of proprietary licensing "solutions" designed to make life as hard for the paying customer as possible, when what the customer really wants to do is make some cool shit with the hardware, and maybe sell a bunch of stuff based on it.
If you're thinking in terms of niches and markets and profit margins, you're thinking about it wrong because you're implicitly assuming that they're not off the wall mad.
SJW n. One who posts facts.
"most people" have no interest in programming FPGAs, so they shouldn't care. "Most people who are into open source CPU design"... they should.
You can think of this as an open source compiler for a closed source piece of hardware: FPGAs already give you the freedom to implement whatever IC you want (e.g a small open source CPU design) - the only closed part about them is the tool chain provided by the FPGA manufacturer and the more unique parts of a particular FPGA hardware beyond the logic block.
This project is interesting because it makes possible something very close to a completely open source CPU process from start to finish without having to go down the ASIC route, and promise of higher quality tools.
I can confirm this statement:
> Anyone who has used one is familiar with the buggy and node-locked accompanying tools that FPGA manufacturers provide
It IS free advertising!
It intrigued me so much that I just bought an evaluation board.
Eval board? Unless you're planning to order 100,000 chips or more, Lattice (or Xilinx, Altera, etc.) really doesn't give a shit.
Actually it works on the 8k chip as well now.
If this stuff was *all* covered by patents, there would be no need at all for reverse engineering. Simple patent searches would suffice.
Many reasons.
They don't want people knowing how good (or how shit) their own tools and FPGAs are compared to others.
They don't want someone to find something in their bitstream format, or FPGA layout that they might have some patent on.
They don't want people to program some broken bitstream into the device, have the thing burn out, and then have people asking for refunds.\
I can think of any number of reasons why they wouldn't want this.
Are they good reasons? That's a different question.
OTOH, perhaps Lattice is currently licensing their POS toolchain, so something like this would mean they have no longer have to license and pay $$$ for the stuff.
Few hardware companies get it - they can produce good hardware, but they invest practically nothing in software - thinking it comes for free or something like it.
Considering Lattice isn't one of the big guys in the whole FPGA business, I'm sure they have to pay Synopsys or Cadence for a lot of the tools. Or provide support to them so customers buy those tools to use their chips.
A project like this would mean they could "own" their own toolchain and be able to provide a low-cost software solution for people to use their chips. And the only reason hardware guys do software is to sell more chips.
Intel already has shittiest crap inside in form of SMX (feature that allows only Intel signed code to run on the CPU and fiddle with private registers that are not accessible otheriwise)
And SGX, feature that comes to Skylake near you will make it possible to create true hardware based DRM, because it will be enforced on CPU level, so unless you hack the chip itself, you couldn't hack it.
ARM is even worse with its TrustZone which is same as SMX but actively abused to lock the shit out of the mobile SoCs including locked bootloader, some of which nobody found a way to hack.
And only God and their CEOs know what backdoors these chips have in addition to this crap
There is one more piece to the game, static timing analysis.
Due to PVT (process, voltage, temperature) variations, proprietary FPGA tools actually check that your logic (when placed & routed) will actually function correctly, that is, signal lengths are not too long so that some signal would come late.
I don't see how you could do static timing analysis without very thorough characterization of the actual FPGA chip.
Of course, if you always overestimate the signal path delays, then you can get something functional, but then it would always be less optimal than if it was compiled and the timing checked with the proprietary tool...
This is cool stuff. Here's some other stuff I found recently for anyone interested in messing with bitstreams, creating an open-source FPGA, or doing hardware more easily. Hardware designers feedback is appreciated.
Open Source Bitstream Generation without R.E. or license violations: http://www.isi.edu/~nsteiner/p...
Archipelago - an open-source FPGA with toolflow support: http://www.eecs.berkeley.edu/P...
Cx, open-source, hardware & synthesis language: http://cx-lang.org/
QFlow Open-source Flow from behavioral synthesis to detail routing: http://opencircuitdesign.com/q...
Have fun people! Especially building on the first two. I'd appreciate experienced people telling me how good the Cx system is for (a) people doing FPGA with high-level synthesis tools and/or (b) beginners using behavioral verilog wanting something better.
In my understanding, one main reason for this secrecy with FPGAs is a kind of DRM. A lot of gadgets out there use FPGAs, and they contain some proprietary design in the form of the bitstream. If this format were open, anyone could copy and modify the design, much more easily than copying actual hardware design of a chip. Thus the secrecy is in the interest of major FPGA users, not the manufacturers themselves.
IIRC, some FPGAs even provide a kind of encryption for bitstreams, but then there's your usual DRM problem of having the keys available somewhere.
Escher was the first MC and Giger invented the HR department.
That is what I was thinking but he does point out that they are insane. I have no evidence to the contrary, so...
"So long and thanks for all the fish."
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I've never actually worked with Lattice, so they might be the rare exception. But yeah most hardware companies seem to be crazy.
SJW n. One who posts facts.
Very interesting that you do DO-254. My background was high assurance and I studied a lot of DO-178B stuff in the process. I didn't work in that market but it generated many high-quality components applicable to other areas. What they pulled off in terms of features amenable to assurance/certification also gave me a guess at what the next project with similar complexity would pull off. Also how I discovered SPARK and Astree. :)
My recent focus is on clean-slate, secure hardware with two aspects being ensuring hardware correctness and preventing subversion. I've come up with a lot of methods applicable to what HW people have taught me of their flows. Safety- and security-critical have considerable overlap in terms of verification from defect reduction to testing to traceability. I'd be very curious to hear of what flow you use for HW (esp ASIC) design in DO-254 space. I appreciate the memo as it's a good start on the subject and will help my own work. Still curious if there is a write-up by anyone on specific flow and what methods worked best on what problems past what's published on HW development in general.