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Seymour Cray and the Development of Supercomputers (linuxvoice.com)
An anonymous reader writes: Linux Voice has a nice retrospective on the development of the Cray supercomputer. Quoting: "Firstly, within the CPU, there were multiple functional units (execution units forming discrete parts of the CPU) which could operate in parallel; so it could begin the next instruction while still computing the current one, as long as the current one wasn't required by the next. It also had an instruction cache of sorts to reduce the time the CPU spent waiting for the next instruction fetch result. Secondly, the CPU itself contained 10 parallel functional units (parallel processors, or PPs), so it could operate on ten different instructions simultaneously. This was unique for the time." They also discuss modern efforts to emulate the old Crays: "...what Chris wanted was real Cray-1 software: specifically, COS. Turns out, no one has it. He managed to track down a couple of disk packs (vast 10lb ones), but then had to get something to read them in the end he used an impressive home-brew robot solution to map the information, but that still left deciphering it. A Norwegian coder, Yngve Ådlandsvik, managed to play with the data set enough to figure out the data format and other bits and pieces, and wrote a data recovery script."
Seymour Cray used the integrated face system to develop super computers.
Seymour Cray in that suit would make for a good Dr Who
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"it could begin the next instruction while still computing the current one, as long as the current one wasn't required by the next "
Doesn't this go without saying?
As the summary and the article fail to mention what COS is, someone should mention that it is the Cray OS.
"Secondly, the CPU itself contained 10 parallel functional units (parallel processors, or PPs), so it could operate on ten different instructions simultaneously. This was unique for the time."
Oh god, this isn't even remotely correct.
For one, a similar design was used by Cray's earlier machine, the CC 6600, which also had 10 PPAs. And by the 7600, and the 8600. For another, there were dozens of machines with similar designs that predate this, including PEPE and the ILLIAC IV, both of which had hundreds of units.
So bogus.
How does one of these supercomputers stack up against a modern amd64 powered computer?
Is one of the 100s of times faster than the other? And which is faster? Is one of them incapable of something the other isn't?
Am past my prime, and maybe getting Old Timers disease...
So can someone remind me, what's the difference between Gene Amdahl and Seymour Cray?
Did they ever meet and have cocktails?
This is an error from the original article, not from the summary. If the author didn't even bother to look up what "PP" actually stood for, I don't have a lot of confidence in the rest of the article's scholarship. Heck, ONE CLICK TO WIKIPEDIA would have given her the proper definition.
I came here to say this. In the early 80's I worked on Control Data Cyber 174C mainframes (we had two). Liquid cooled, about maybe 20 feet long with hinged chassis that swung out like doors (maybe 40" by 6' and about 10" thick) . One chassis was a CPU, two were memory I think, and one was for 10+ Peripheral Processor Units (PPUs) which did 100% of the I/O. A whopping 40 MHz! and a 208 bit memory bus with SECDED.
I interned (sort of) at Babcock and Wilcox's computing center around 1980. We had several CDC systems, including a 76 ("7600"), which was built in a horseshoe arrangement much like the Cray-1. (The field engineers used its interior as a storage closet.) Me, I was just hauling tapes, card decks and printouts, but I did get to learn a bit about the machines, and a lot more once I got into comp architecture classes in college. It was a great place for a geek.
I worked with the CDC 6400 at the University of Colorado. It had an Extended Core Storage unit, a separate cabinet full of magnetic cord memory (they came up to 2 M words; I don't know how large CU's was). We gave machine room tours, including opening the door on the ECS, until somebody noticed that the machine sometimes crashed when the door was shut. Don't want to jiggle those cores, I guess. Just found this: http://www.corememoryshield.com/report.html
Or, you can just write it in C, and let the compiler do all that nitty, gritty detail stuff. Let the architecture have funky stuff, and a small transistor count.
PPs were "Peripheral Processors." There were 10 virtual units that handled mostly I/O tasks for the operating system. In hardware they were implemented as a rotating "barrel" of 10 processor states (registers, etc.) that, on each clock tick, could initiate one instruction for one of the PPs. Just this level of ignorance gives me doubts about the quality of the whole article.
I taught CDC600 assembly language for a couple of semesters. That software was a joy to use. Since there were only 61 op codes, the assembler had macros of course, but also "micros" that could substitute text within a source code instruction. A standard exercise was to develop an interface that dealt with the calling conventions of more than one higher-level language compiler automatically. Lots of fun.
Right on. I worked at Control Data, as a CPU logic designer. The PP's were peripheral processors. The article is full of so much egregiously incorrect tripe I won't even bother to type up a correction. My advice to everyone is to completely ignore the article unless you want your head stuffed full of misinformation.
Introduction to/History of computers classes.
I ended up putting it off until my last sem of college (including a couple of higher level classes I actually wanted to take, which required it as a prereq) The class was so full of technical and historical inaccuracies (Especially PC era ones, many of which I heard about as they were happening) that the professors were willing to ignore (in this particular college's case because lower division comp-sci classes were actually from business rather than EE or Mathematics departments.)
I checked in on it *10* years later and the same crap was being shovelled off, but in a fresh new (more expensive) book, with e-book only options coming the following year.
Lament the history you lived through, because it is being systematically rewritten by people who should neither be labelled historians, nor technically knowledgable.
P.S. If you can, you might want to start documenting your own history or pieces of others that you remember clearly, so it can be corraborated against other's statements in the future in the hopes of one day providing a clearer picture of the history of the modern mainframe to microcomputer... and beyond.
Too bad the LinuxVoice article didn't link to Chris Fenton's work on his "desktop Cray": http://hackaday.com/2010/09/29/tiny-cray-1-courtesy-of-an-fpga/
(There are followup articles on Hackaday about the software issues too.)
The multiple functional units idea wasn't new with Cray's supercomputer. He was doing much the same thing in the computers he designed for Control Data Corporation (CDC).
Also, it seems astonishing that there would be no copies of that Cray software around, anywhere, other than on an old disk pack. There are still copies of the software for those CDC machines. Maybe that's because there were so many of them -- relative to the Crays.
There's no time like the present. Well, the past used to be.
Just started to RTFA, and spotted two goofs.
My goof: The quoted text _was_ about the CDC 6600. That certainly explains the similarity.
The article's goof: Those were peripheral processors, not "parallel processors". They did I/O and occasional odd jobs for the operating system that the CPU wasn't suited for, or too busy to do.
Now to finish it off, and see what else I or the author have to be embarrassed about.
There's no time like the present. Well, the past used to be.
Itanium, I suppose.
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