I've worked in detail with a VLIW (Very Long Instruction Word) architecture, the TI 'C6x DSP. It has eight execution units (not all of which can perform the same operations, though there is a little overlap) which can all be active in a single cycle. However, the key is keeping all of the units busy.
While the C compiler for this architecture is incredibly good, there are situations where using raw assembly (quite hard because of pipelining issues) or "compiled assembly" (easier, since you write in the order you wish operations to occur, and the compiler schedules the pipeline for you) gives better performance.
In short, no matter how much hardware folks can throw at a computing problem, the issue is adapting lots of different kinds of software to the architecture. Sounds like the compiler is going to have to be very good, or else there will have to be some runtime mojo to keep all of the chip doing something useful.
Intel has specified that the traces for its FSB layout be as compact as possible in order to prevent retarding hole propagation. They call it the "Short Bus" protocol.
So what you're saying is that you really like monkeys who eat strawberries for dinner?
Your comment is oh-so PoMo and oh-so indefensible. By your own lights, my above analysis of your comment is just as accurate as any other.
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I've worked in detail with a VLIW (Very Long Instruction Word) architecture, the TI 'C6x DSP. It has eight execution units (not all of which can perform the same operations, though there is a little overlap) which can all be active in a single cycle. However, the key is keeping all of the units busy.
While the C compiler for this architecture is incredibly good, there are situations where using raw assembly (quite hard because of pipelining issues) or "compiled assembly" (easier, since you write in the order you wish operations to occur, and the compiler schedules the pipeline for you) gives better performance.
In short, no matter how much hardware folks can throw at a computing problem, the issue is adapting lots of different kinds of software to the architecture. Sounds like the compiler is going to have to be very good, or else there will have to be some runtime mojo to keep all of the chip doing something useful.
Intel has specified that the traces for its FSB layout be as compact as possible in order to prevent retarding hole propagation. They call it the "Short Bus" protocol.
So what you're saying is that you really like monkeys who eat strawberries for dinner? Your comment is oh-so PoMo and oh-so indefensible. By your own lights, my above analysis of your comment is just as accurate as any other.
8GHz and 640kB are all anyone will ever need. (Yes, I've read Snopes about this)