Intel vs AMD architecture: Intel works with a long "pipeline" system that breaks up a command into a large number of short commands (memory moves, compares, etc) and can be on the order of 52 stages. Once this pipeline is loaded with commands (say 52 of them) it will seems to be executing a command every clock cycle; however the time to process a single command is longer
AMD works with a shorter pipeline of longer tanks (say 20 stages) so a single command will execute faster but under heavy loads it can seem to take longer to execute.
As a side note SUN works with a large number of simple cores because their systems are tailored to a large amount of parallel processing.
AMD chip porn: For those that do not know what they are looking at here is my best guess. The squares are memory cells: the dull ones are high speed buffers and the shiny ones are cache. The cache in the middle is the L2 discussed earlier in the article (16k blocks I think) and the blocks at the bottom of the image are the L3 cache (16k blocks). The block size depends on where you draw the border between blocks as the bars in the cells are the buses so a "block" could be made of four visual blocks to allow for faster access (reduce distance between cell and bus)
On chip vs Off chip memory: One issue that arises with off chip memory is clock speed options. Due to the speed of light a 3.3 Ghz signal has a 10cm wavelength, and according to Nyquist we should sample at twice that so really only 5cm is usable with perfect electronics. This does not take into account settling times and the power this would require to move a voltage that fast (will spare you the math). There is also all the buffering and caching hardware required to communicate off chip not to mention issues of synchronizing the two devices (clock jitter between devices, etc). The reason this is not always an option is because memory is large and real estate is precious.
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Intel vs AMD architecture:
Intel works with a long "pipeline" system that breaks up a command into a large number of short commands (memory moves, compares, etc) and can be on the order of 52 stages. Once this pipeline is loaded with commands (say 52 of them) it will seems to be executing a command every clock cycle; however the time to process a single command is longer
AMD works with a shorter pipeline of longer tanks (say 20 stages) so a single command will execute faster but under heavy loads it can seem to take longer to execute.
As a side note SUN works with a large number of simple cores because their systems are tailored to a large amount of parallel processing.
AMD chip porn:
For those that do not know what they are looking at here is my best guess.
The squares are memory cells: the dull ones are high speed buffers and the shiny ones are cache. The cache in the middle is the L2 discussed earlier in the article (16k blocks I think) and the blocks at the bottom of the image are the L3 cache (16k blocks). The block size depends on where you draw the border between blocks as the bars in the cells are the buses so a "block" could be made of four visual blocks to allow for faster access (reduce distance between cell and bus)
On chip vs Off chip memory:
One issue that arises with off chip memory is clock speed options. Due to the speed of light a 3.3 Ghz signal has a 10cm wavelength, and according to Nyquist we should sample at twice that so really only 5cm is usable with perfect electronics. This does not take into account settling times and the power this would require to move a voltage that fast (will spare you the math). There is also all the buffering and caching hardware required to communicate off chip not to mention issues of synchronizing the two devices (clock jitter between devices, etc). The reason this is not always an option is because memory is large and real estate is precious.