Both are awful languages from a theoretical standpoint. Practically, the synthesis subset accepted by RTL tools renders them almost identical, although their spirits are actually quite different. VHDL is more verbose but has the more rigorous type system. I chose to teach it based more-or-less on a coin flip. Whatever you choose, your students' first employers will be using the other one, so it doesn't really matter.
My class at Columbia can be found at
http://www1.cs.columbia.edu/~sedwards/classes/2009/4840/
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Both are awful languages from a theoretical standpoint. Practically, the synthesis subset accepted by RTL tools renders them almost identical, although their spirits are actually quite different. VHDL is more verbose but has the more rigorous type system. I chose to teach it based more-or-less on a coin flip. Whatever you choose, your students' first employers will be using the other one, so it doesn't really matter. My class at Columbia can be found at http://www1.cs.columbia.edu/~sedwards/classes/2009/4840/