Since the "normal workload for an ultra-portable" isn't that much anyhow like you've said, then the performance difference is moot because it's not that big of a gap anyways....and by the same token, who in the world is going to use "ultra-portable" as "desktop replacement"? Pbbt.
Germany is a long way from Santa Clara. The fact remains that the original poster typed "Pat Gelsinger recently revealed that Larrabee's 32 IA cores will in fact be based..." instead of "Speculations are that..."
I see the thread as "extreme sloppy reporting and non-checking by all parties" followed by "a massive episode of base-jumping related lemming deaths".
"Gelsinger said the Larrabee will be a 45nm product featuring SIMD technique, 64-bit address. Besides, 32 of cores runing at 2.00 GHz will unleash 2 TFLOPS capacity, twice as much as the RV770XT."
It seems that no matter which crappily translated version of the German article one looks at, it appears that Gelsinger said no such thing... The part about Larrabee containing P54C cores was clearly in a separate paragraph, written after a speculative question.
So I guess Expreview THOUGHT Pat said something after it took a too-short of a look at the Heise article, after which CustomPC sensationalized the whole thing, not really bothering to actually read even the translated link it posted. Now, some random Slashdotter is doing the same curtesy.
There is no "Soyuz Capsule Culture" that is trying to introduce a "new space hardware culture change", and there's no resistance to this non-existent "Soyuz Capsule Culture".
AMD fellow Elsie Wahlig posted the following on a Linux mailing list:
AMD Family 10h revision B2 processors suffer from an issue in the
processor TLB known as erratum 298. Erratum 298 is documented in
a forthcoming update to the Revision Guide for AMD Family 10h
Processors (PID 41322). The workaround in the Revision Guide
document is intended to be applied by BIOS. The BIOS workaround
has performance implications which can be avoided by having the
OS directly workaround the issue. A Linux 64-bit patch was developed
for 2.6.23.8 by AMD's OSRC team and will be posted to this list by
Joerg Roedel. The patch is for demonstration purposes and is NOT
being recommended to be applied upstream.
Erratum 298 will be described as follows: "The processor operation
to change the accessed or dirty bits of a page translation table
entry in the L2 from 0b to 1b may not be atomic. A small window of
time exists where other cached operations may cause the stale page
translation table entry to be installed in the L3 before the modified
copy is returned to the L2. In addition, if a probe for this cache
line occurs during this window of time, the processor may not set
the accessed or dirty bit and may corrupt data for an unrelated
cached operation. The system may experience a machine check event
reporting an L3 protocol error has occurred. In this case, the MC4
status register (MSR 0000_0410) will be equal to B2000000_000B0C0F
or BA000000_000B0C0F. The MC4 address register (MSR 0000_0412) will
be equal to 26h."
The L2 Eviction Linux kernel performance patch re-enables the
registers set for the BIOS workaround described in the Revision
Guide document. It then prevents the processor from performing the
operation that can trigger erratum 298. The patch works by emulating
the Accessed and Dirty bits.
The basis for the kernel patch solution depends on the root cause of
the L2 eviction problem. The only exposure for the problem is when
the TLB needs to set an A or D bit in a page table entry. If the TLB
never needs to set an A or D bit, the bug cannot occur. By emulating
the A and D bits with the help of the Present and Writable bits, the
patch will ensure the real A and D bits are always preset. It works
by forcing a page fault when the first access is made to a page with
the emulated A bit not set, and when the first write access is made
to a writable page with the emulated D bit not set. Emulated A and D
bits are stored in bits generally available to the OS in the page
table entry.
Slashdot Mirror
Correction- Wikipedia said he was employee number 3. He's still not a co-founder, however.
Intel was founded by Gordon Moore and Robert Noyce. I think Andy Grove was employee number 5.
Since the "normal workload for an ultra-portable" isn't that much anyhow like you've said, then the performance difference is moot because it's not that big of a gap anyways. ...and by the same token, who in the world is going to use "ultra-portable" as "desktop replacement"? Pbbt.
Germany is a long way from Santa Clara. The fact remains that the original poster typed "Pat Gelsinger recently revealed that Larrabee's 32 IA cores will in fact be based..." instead of "Speculations are that..." I see the thread as "extreme sloppy reporting and non-checking by all parties" followed by "a massive episode of base-jumping related lemming deaths".
http://babelfish.yahoo.com/translate_url?doit=done&tt=url&intl=1&fr=bf-home&trurl=http%3A%2F%2Fwww.heise.de%2Fct%2F08%2F15%2F022%2F&lp=de_en&btnTrUrl=Translate
Actually, they got the "Gelsinger said so" remark from Expreview, itself a Chinese site:
http://en.expreview.com/2008/07/07/larrabee-unleashes-2-tflops-capacity (note they curteously attached the Larrabee board diagram leaked from a while back):
"Gelsinger said the Larrabee will be a 45nm product featuring SIMD technique, 64-bit address. Besides, 32 of cores runing at 2.00 GHz will unleash 2 TFLOPS capacity, twice as much as the RV770XT."
But did Gelsinger really SAID those things?
Here is the Google translation of the same Heise article: http://translate.google.com/translate?u=http%3A%2F%2Fwww.heise.de%2Fct%2F08%2F15%2F022%2F&hl=en&ie=UTF8&sl=de&tl=en
It seems that no matter which crappily translated version of the German article one looks at, it appears that Gelsinger said no such thing... The part about Larrabee containing P54C cores was clearly in a separate paragraph, written after a speculative question.
So I guess Expreview THOUGHT Pat said something after it took a too-short of a look at the Heise article, after which CustomPC sensationalized the whole thing, not really bothering to actually read even the translated link it posted. Now, some random Slashdotter is doing the same curtesy.
There you go, folks- Internet reporting.
There is no "Soyuz Capsule Culture" that is trying to introduce a "new space hardware culture change", and there's no resistance to this non-existent "Soyuz Capsule Culture".