Because the P4 architecture has hooks for SMT (Simultaneous Multi Threading) or what the Intel loons call Hyperthreading. Instead of exploiting ILP, it will support multiple thread contexts executing simultaneously. The proc can perform a thread switch when one thread stalls waiting for a TLB or cache spill, maybe even a bad branch mispredict and allow the cleanup to take multiple cycles. At that point, I'm sure you'll whine bitch and moan because it will not be clocked as high but will still be doing more work. Reading Tom's Hardware does not a guru make. I sure as hell am not one.
No idea how/if they will push SMT into IA64. Predication, prefetching and speculative store/restoring register windows should mitigate more pipeline stalls. But only time (or a fat red cover NDA) will tell.
Do you compile your own software or rely on others to do so for you? Linking _large_ applications will frequently take massive amounts of memory.
But most people out there haven't compiled anything larger than the linux kernel which has been careful about their namespaces.
Hopefully the GCC crew will get their act together and do more block and global optimizations. The graph setup for those will be immense.
As networking speeds increase, you'll need more and more memory to buffer connections. TCP reliability isn't free. IPv6 jumbograms may exacermate the requirement.
.TROLL
If you need to ask, you're not bright enough to do anything complex anyway -- say a crashdump when you screw up doing kernel devel.
Clock speed is only relevant to marketing droids and those stupid enough to believe them.
The are processors (UltraSparc III) where the core pipeline is not clocked (called wave pipelining). There are caches that are double pumped; they do work on each edge of the clock instead of only latching on one edge.
And an even clearer fact: different processors do different amounts of work per edge of the clock. If you want a _really_ high clock rate, put only one gate between each latch. That clock rate would be obscene. But half of the work done would be latching the values (assuming you could distribute the clock over so large an area).
If you want to normalize anything, normalize over price. Unless you have stupid friends and compete over having the highest clock.
Oh ya. Don't bother talking about FLOPS or MIPS. You'll just end up sounding stupid (and you need all the help you can get). Any benchmark not targetted to YOUR specific application is next to worthless.
Heh, some processors don't even bother to dispatch NOPs. With a little hackert, they could ``execute'' as many NOPs per clock as the depth of their dependancy issue window.
They are not considered unsolvable. They are considered intractable problems for the design time required by the industry. Asynch logic is one of the first things taught in the Digital side of EE. But those are small projects, _far_ fewer than the millions of transistors required my a modern micro.
UltraSparc III actually is partially asynch. The core pipeline uses a technique called ``Wave Pipelining'' which doesn't latch between pipeline stages. IIRC, one of the Alpha processors didn't have latches between the L1 cache pipeline stages.
Since the P6 core was introduced with the Pentium Pro, the processor could access 64GB of physical memory. The PTE's (Page Table Entries) have a 36bit wide space for the physical address. You can still only access 32bits of space at a time in a single application since the virtual address space is only 32 bits wide.
It remains to be seen if IA64 can really have that much physical memory. IIRC, SUN4U only has 40 address pins on the CPU.
The only VoIP protocol that a majority of firewalls supports is Netmeeting.
There is a push (albeit small) for more firewalls to support h.323 in general. Unfortunately, h.323 is like FTP in that it opens auxiliary connections to random ports so it takes alot of processing per connection. And to top it off, the control channel uses ASN.1 like SNMP.
ASN.1 fields are variable length, ie: Byte 1 : Variable type (integer, string..) Byte 2 : Length of variable -- this is also a variable length field. Byte 3 : The actual variable Data. Byte 4 : The next variable type.
So you esentially have at least one branch statement per byte in a packet. And the variables of importance to firewalls may be buried several deep. Lots 'o processing.
Don't ask me how you plan to connect to someones internet phone behind a firewall. VoIP in a semisecure environment is like a one way phone. You can call people but they can't call back. Ideal if you ask me;)
While scanning the cosmos looking for the intangible, what beverage do you consume?
If you discovered little green men barreling around our galaxy at sub-light speed, how would your beverage of choice change? Same question, but if you discovered a class M planet?
Do you believe the consumption of a particular beverage during the course of a scientific investigation directly correlates to the results obtained?
No mathmatical proofs please, I'm still nursing my third cup of coffee.
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Because the P4 architecture has hooks for SMT (Simultaneous Multi Threading) or what the Intel loons call Hyperthreading. Instead of exploiting ILP, it will support multiple thread contexts executing simultaneously. The proc can perform a thread switch when one thread stalls waiting for a TLB or cache spill, maybe even a bad branch mispredict and allow the cleanup to take multiple cycles. At that point, I'm sure you'll whine bitch and moan because it will not be clocked as high but will still be doing more work. Reading Tom's Hardware does not a guru make. I sure as hell am not one.
No idea how/if they will push SMT into IA64. Predication, prefetching and speculative store/restoring register windows should mitigate more pipeline stalls. But only time (or a fat red cover NDA) will tell.
I've borrowed the book from my boss every time I have to do something wierd with CVS. It has never answered my question.
It may be a good primer but there is an overabundance (but scattered) free documentation out there already
Do you compile your own software or rely on others to do so for you? Linking _large_ applications will frequently take massive amounts of memory.
But most people out there haven't compiled anything larger than the linux kernel which has been careful about their namespaces.
Hopefully the GCC crew will get their act together and do more block and global optimizations. The graph setup for those will be immense.
As networking speeds increase, you'll need more and more memory to buffer connections. TCP reliability isn't free. IPv6 jumbograms may exacermate the requirement.
.TROLL
If you need to ask, you're not bright enough to do anything complex anyway -- say a crashdump when you screw up doing kernel devel.
Clock speed is only relevant to marketing droids and those stupid enough to believe them.
The are processors (UltraSparc III) where the core pipeline is not clocked (called wave pipelining). There are caches that are double pumped; they do work on each edge of the clock instead of only latching on one edge.
And an even clearer fact: different processors do different amounts of work per edge of the clock. If you want a _really_ high clock rate, put only one gate between each latch. That clock rate would be obscene. But half of the work done would be latching the values (assuming you could distribute the clock over so large an area).
If you want to normalize anything, normalize over price. Unless you have stupid friends and compete over having the highest clock.
Oh ya. Don't bother talking about FLOPS or MIPS. You'll just end up sounding stupid (and you need all the help you can get). Any benchmark not targetted to YOUR specific application is next to worthless.
Heh, some processors don't even bother to dispatch NOPs. With a little hackert, they could ``execute'' as many NOPs per clock as the depth of their dependancy issue window.
They are not considered unsolvable. They are considered intractable problems for the design time required by the industry. Asynch logic is one of the first things taught in the Digital side of EE. But those are small projects, _far_ fewer than the millions of transistors required my a modern micro.
UltraSparc III actually is partially asynch. The core pipeline uses a technique called ``Wave Pipelining'' which doesn't latch between pipeline stages. IIRC, one of the Alpha processors didn't have latches between the L1 cache pipeline stages.
Since the P6 core was introduced with the Pentium Pro, the processor could access 64GB of physical memory. The PTE's (Page Table Entries) have a 36bit wide space for the physical address. You can still only access 32bits of space at a time in a single application since the virtual address space is only 32 bits wide.
It remains to be seen if IA64 can really have that much physical memory. IIRC, SUN4U only has 40 address pins on the CPU.
The only VoIP protocol that a majority of firewalls supports is Netmeeting.
;)
There is a push (albeit small) for more firewalls to support h.323 in general. Unfortunately, h.323 is like FTP in that it opens auxiliary connections to random ports so it takes alot of processing per connection. And to top it off, the control channel uses ASN.1 like SNMP.
ASN.1 fields are variable length, ie:
Byte 1 : Variable type (integer, string..)
Byte 2 : Length of variable -- this is also a variable length field.
Byte 3 : The actual variable Data.
Byte 4 : The next variable type.
So you esentially have at least one branch statement per byte in a packet. And the variables of importance to firewalls may be buried several deep. Lots 'o processing.
Don't ask me how you plan to connect to someones internet phone behind a firewall. VoIP in a semisecure environment is like a one way phone. You can call people but they can't call back. Ideal if you ask me
While scanning the cosmos looking for the intangible, what beverage do you consume?
If you discovered little green men barreling around our galaxy at sub-light speed, how would your beverage of choice change? Same question, but if you discovered a class M planet?
Do you believe the consumption of a particular beverage during the course of a scientific investigation directly correlates to the results obtained?
No mathmatical proofs please, I'm still nursing my third cup of coffee.