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User: jandecaluwe

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  1. Re:Not a fan of procedural languages syntax for HD on Learn Gate-Array Programming In Python and Software-Defined Radio · · Score: 1

    To all those who equate MyHDL with "procedural input", just because it is pure Python, please hold your horses for a minute.

    HDLs like Verilog and VHDL have both procedural and concurrent semantics. The concurrent part is very specific: fine-grained, massive, but tightly controlled through event-driven semantics. The only thing necessary to emulate that in Python are generators (functions with state), which is a pure Python concept , and an event-driven scheduler (implemented in a Simulation object).

    As a result, the semantics of MyHDL, in particular its concurrent semantics, are basically identical to Verilog and VHDL semantics.

  2. MyHDL on VHDL or Verilog For Learning FPGAs? · · Score: 1

    Why not consider a HDL for the google generation :-)

            http://www.myhdl.org/doku.php

    This is Python used as a HDL - conversion to Verilog and VHDL included!

    Jan