... reprising his role as the T1000 (disguised as a traveller from a post-apocalyptic future, hmm), in a desperate attempt by the suits at Fox to resurrect the show.
because their chip probably just plugs into the PCI bus (maybe directly to the memory as well if they feel adventurous) and does hardware compression of disk caching. Probably intercepts DMA transactions, keeping track of commonly requested sectors, bookkeeping on compressed data, and bypasses the disk if the data is available in the compressed buffers.
The driver will probably disable OS built-in disk caching, and install some interrupt handlers to grow and shrink the cache, do replacement policy, etc, when things start to thrash.
If true, then the codec will not increase memory latency, but it will steal bus cycles somewhere, but since the OS itself no longer caches the disk, probably not more cycles than before. There will be an increase in disk latency, but again since the OS caching step is eliminated, no additional latency is incurred. Not like this really matters.
Just reread the article after reading some more posts, and it turns out my component placement was completely off. This thing sounds more like a HD controller hack to add hardware compression to read buffers, which would explain why it wouldn't be too cool for consumer boards (try fitting this on integrated chipset IDE)... And, I forgot to consider the power reduction from not having to power the IDE interface and HD.
If they figured out a way to efficiently and transparently compress pages without nailing performance and cost (internal/external fragmentation problems, lots of on-chip ram in the codec to hold data structures...), I would be a lot more impressed. I also want to know how much control is given to the OS for partitioning memory between paging space and buffer space for the codec, very important in estimating the exact effects on the OS/HW. I'm eagerly waiting the benchmarks/details.
"MXT incorporates a new level of cache designed to handle data and instructions on a memory controller chip.", ie strictly more hardware and bus traffic, so the power drain for IBM's present implementation must be higher if the same number of DRAMs are used.
Power consumption can actually drop if the codec logic is placed directly on the DRAMs and chipset, such that only compressed data goes over the system bus. Pushing signals on off-chip busses takes a good amount of juice, and having 1/2 the number of DRAM chips adding parasitics to the memory busses helps a lot too...
The profits of component manufacturers haven't been keeping up with the rest of high tech. I'm wliling to bet this deal gives Toshiba (and probably anyone else willing to settle with Rambus) the opportunity to pad their own wallets. Smells like the beginning of an industry price-fixing cycle... -nh4no3 [The opinions expressed are mine and not those of Intel Corporation]
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Silly cow, global warming is the only thing holding back the Ice Age!
... reprising his role as the T1000 (disguised as a traveller from a post-apocalyptic future, hmm), in a desperate attempt by the suits at Fox to resurrect the show.
The driver will probably disable OS built-in disk caching, and install some interrupt handlers to grow and shrink the cache, do replacement policy, etc, when things start to thrash.
If true, then the codec will not increase memory latency, but it will steal bus cycles somewhere, but since the OS itself no longer caches the disk, probably not more cycles than before. There will be an increase in disk latency, but again since the OS caching step is eliminated, no additional latency is incurred. Not like this really matters.
-nh4no3
If they figured out a way to efficiently and transparently compress pages without nailing performance and cost (internal/external fragmentation problems, lots of on-chip ram in the codec to hold data structures...), I would be a lot more impressed. I also want to know how much control is given to the OS for partitioning memory between paging space and buffer space for the codec, very important in estimating the exact effects on the OS/HW. I'm eagerly waiting the benchmarks/details.
-nh4no3
Power consumption can actually drop if the codec logic is placed directly on the DRAMs and chipset, such that only compressed data goes over the system bus. Pushing signals on off-chip busses takes a good amount of juice, and having 1/2 the number of DRAM chips adding parasitics to the memory busses helps a lot too...
-nh4no3
The profits of component manufacturers haven't been keeping up with the rest of high tech. I'm wliling to bet this deal gives Toshiba (and probably anyone else willing to settle with Rambus) the opportunity to pad their own wallets. Smells like the beginning of an industry price-fixing cycle... -nh4no3 [The opinions expressed are mine and not those of Intel Corporation]