I've been working in the spam-fighting industry (sad that this actually is an industry now!) for a few months now, and that's the one question that's been bothering me.
My conclusion: It's NOT profitable!
Sure, there are the few people who SEND spam that make lots of money, but by and large, the people actually trying to sell stuff by spam are losing money.
Everyone always talks about how cheap it is to send tons of spam, but cheap or not, it still costs SOME amount of money. The big spammers spend thousands of dollars a month (or more) just for their internet connections, while the small-time spammers sending from their DSL connections can only get out, at best, about 100,000 messages before their connection is killed.
But despite that, there is a LOT of spam, a REALLY large quantity of it. I did some rough estimates and figured that there is at least 10 billion spam messages being sent each and every day (Hotmail alone receives roughly 2 billion spam messages a day). Even at a cost of only $10/million messages (and I'd wager that the costs I've seen are at least 10 times that much), we're talking about spammers spending hundreds of thousands of dollars a day!
Now, some of this might be profitable, particularly some of the porn spam, the ones that really get me though are the thing like all the penis enlargement spam. These so-called "penile-enhancement" pills make up probably 5-10% of all spam. I'd figure at a minimum spammers are spending $10,000 a day sending out penis enlargement spam. Now, I realize that PT Barnum told us that there are suckers born every minute, but there honestly are just not that many complete and utter morons born every second to make this sort of thing possible!
The real trick though is that some companies have made a lot of money selling spam. They've managed to convice the suckers that are born every minute that simply sending out penis-enlargement spam ads to millions of people will make them money. End result, the people actually trying to sell stuff by spam are losing money by the boatload, but there are are just too many dumbasses on the planet! Even after thousands have lost money sending this spam before them, people are still lining up to be the next one to send you a penis enlargement spam because they're absolutely certain that they'll exploit the "dumb masses" and make tons of money.
FWIW Cyrix is dead in all but the name, and even that is pretty much gone. Cyrix as a seperate entity disapeared some time ago when they were bought by National Semi. NS then proceeded to mismange, bungle and thwart all attampts to do anything useful for the next two+ years, before finally giving up and selling the Cyrix MII processor, the Cyrix name and most Cyrix employees to VIA. NS kept the MediaGX chip to themselves, and still sell it, albeit it in virtually non-existant quantities.
As for VIA, they sold the MII for a short time, but that was the ONLY Cyrix chip they ever sold, and it didn't last that long. They basically sacked the entire Cyrix development teams and have now dropped the Cyrix name as well in favor of the names like "VIA C3". As for the chips, these are actually designed by the old IDT/Centaur "Winchip" design team, which VIA bought at almost the same time as their Cyrix purchase.
That'sa reasonably good point, though I don't anticipate Transmeta making too much of a dent here any time soon. The higher bandwidth memory and Hypertransport bus on the new Astro migh help, but they really need to get the performance of the chip up to half-way respectable levels first.
However, the Pentium-M looks like a KICK-ASS blade server processor to me! Beyond the low power consumption, it has 1MB of L2 cache! What's more, it's got a 400MHz bus, which should help for some decent I/O performance. Combine that with a fairly powerful CPU core, and you've got quite a very nice solution.
How much would you pay to get rid of the noise your computer makes?
Not much, fortunately. VIA's C3 processors consume roughly the same amount of power that the Transmeta chips consume, they sell for a fraction of the price, they are reasonably easy to find, they work on TONS of motherboards (most modern P3 boards), and to top it off, they beat the pants off anything Transmeta's put out when it comes to performance (which isn't saying much).
Yup, the systems will be NUMA. However, AMD is trying to coin a new phrase for their chips, SUMO (Sufficiently Uniform Memory Organisation, I think). They even have a little drawing of a sumo wrestler on some of their documents:>
The idea is that they will use their Hyptertransport links as a high-speed, cache-coherant, memory bus. Their claim is that the interconnect links will have enough bandwidth and sufficiently low latency that you can completley ignore the fact that it's a NUMA system and treat it exactly the same as a UMA system.
In reality, the chips will probably benefit from some NUMA optimizations, however the setup does look pretty good. Typically accessing remote memory will still be just as fast as accessing memory through an external memory controller, as is done in all current x86 systems.
That's actually a very good question, since the rumors as to the difference seem to change about every second day!
Originally there were two chips, the Sledgehammer and the Clawhammer. The Sledge had 1MB of L2 cache, 3 Hypertransport links and a 128-bit wide memory controller. The Clawhammer had 256KB of L2 cache, 1 Hypertransport link and a 64-bit wide memory controller.
At first it seemed like the Sledgehammer was just going to get the official name of "Opteron" while the Clawhammer would get the official name of "Athlon64". However, it no longer seems that simple, since there are THREE different versions of the Opteron (the 100, 200 and 800 series models). What's more, it's looking like AMD might shy away from using only 256K of cache on their desktop chip since Intel will just be releasing new desktop chips with 1MB of cache at the same time.
So, where does that leave us? Well, I dunno for sure, but this is my guess:
Opteron 100 series: 1MB of cache, 1 Hypertransport link, 128-bit wide memory bus, only for single processor systems Opteron 200 series: 1MB of cache, 2 Hypertransport links, 128-bit wide memory bus, for dual-processor systems Opteron 800 series: 1MB of cache, 3 Hypertransport links, 128-bit wide memory bus, for up to 8-way SMP systems
Athlon64: 1MB of cache, 1 Hypertransport link, 64-bit wide memory bus, only for single processor systems "Athlon64-Lite" (Duron64?): 256KB of cache, 1 HT link, 64-bit memory bus, single-processor only.
Of course, it could be a bit trickier than that. Also, I've seen documents from AMD where their "single" 16-bit Hypertransport link could be split into two 8-bit HT links and allow for dual-processor operation. So, perhaps the Opteron 100 and Opteron 200 series will be identical except that the latter will be certified for use in dual-processor systems? If this is the case, than the Athlon64 would also (at least theoretically) work in dual-processor systems.
It's also quite possible that AMD will have one or more processor with 512K of cache, rather than the 256K or 1MB originally planned.
Long story short, until AMD announced the official specs, no one really knows for sure.
No, the pointers are still 64-bits, it's just that the top ~20 of those bits will be rather useless for the time being (the Opteron supports 40-bit physical addresses, but something like 45 virtual address lines). The previous poster was correct, the idea behind this was that the number of pins for the address bus.
To answer the previous poster's question, yes, the chip can be expanded to right up to the full 64-bits of physical address space without any changes to the ISA.
AMD's Opteron processor will be offered in three varieties:
Opteron 1xx series - Single processor workstations/servers Opteron 2xx series - Dual processor workstations/server Opteron 8xx series - Up to 8-way SMP servers
The first two are pretty directly targeting the market that the Xeons currently sell into, but the last one starts to touch on the Itanium's market. The Xeon tends not to scale well beyond 2 processors, and in fact, most Xeons won't work at all in anything more than 2-way systems (only the Xeon MP is certified for use in 4+ processor systems).
As for price, AMD hasn't announce any prices, but I think it's quite reasonable to assume that the 1xx series of Opterons will be quite reasonably priced (probably not significantly more than an AthlonXP or P4), the 2xx series will be priced similar to the Xeon (about 10-20% more than a P4 of the same clock rate), while the 8xx chips will cost about the same as a Xeon MP ($1000-$2000).
Of course, when it comes to servers, the processor is only one relatively small part of the equation, and so far all the Opteron servers I've seen have been pretty high-end systems, so I don't expect them to be cheap.
First off, every x86 chip since the original Penium have used 64-bit buses anyway! ie they reversed the old 386SX, using 32-bits internally, but 64-bits externally.
The next problem in your theory is that the Hammer completely changes all the rules about buses anyway (at least the x86-rules of buses). The processor will have an on-die memory controller, which basically eliminates most of the traffic that went over a traditional bus. In current x86 systems, there is only one bus that transports both the memory data and I/O data. In Hammer systems, there will be two or more buses, one for memory and 1 to 3 of them for all other I/O. Ironically, these I/O buses will be reduced down to 16-bits, though they run at quite high speeds and offer comperable bandwidth to today's 64-bit buses (this is what AMD calls Hypertransport).
The most important reason though is simply that motherboards are dirt-cheap these days, and demand for upgrade chips is such a tiny market that it's totally trivial and can be very easily ignored (which is sometimes kind of annoying for the odd-balls like myself who might actually buy such a product!)
Obviously you didn't bother reading the article before posting did you? I guess I shouldn't expect that though.
While it is true that 32-bit x86 chips can address 36-bits of memory using Intel's PAE, they do so using a really ugly hack. It was a really ugly hack back in the 16-bit x86 days, and it's still an ugly hack now.
AMD's solution is the right one, a true flat 64-bit address space. 64-bit integers aren't particularly important, it's quite rare that an application needs 64-bit integers, and when they do they can easily be handled with two 32-bit integers (albeit at a significantly reduction in performance as compared to true 64-bit integers). 64-bit addressing is what x86 is all about. Well, that and clearing up a few of the remaining problem spots in x86, ie doubling the registers and getting rid of some mostly-useless modes.
It's 40% by the number of messages, and you're definitely right about spam messages being, on average, much larger than non-spam messages. At a rough guess, I'd say that by % of total size, spam would make up somewhere around 70-80% of all e-mail traffic.
FWIW the 40% number is probably a reasonably good cross-section of ALL internet e-mail sent (it wouldn't count internal company e-mail). Presumably it takes into account all of Brightmail's customers. A lot of Brightmail's customer's are corporations blocking their company mail, which have much lower levels of spam than personal e-mail accounts. However Brightmail also has a LOT of major ISPs using their filtering software, eg MSN / Hotmail, AT&T WorldNet, Earthlink, etc. These customers see much higher percentages of spam.
Just as a FWIW, I know for a fact that Hotmail regularly blocks over a billion spam messages a day, though exact numbers are slightly tough to compare since Hotmail counts their messages differently than AOL does (1 message to 100 address = 1 message for Hotmail vs. 100 messages for AOL as I understand it). In total, Hotmail gets about 2.3 billion messages a day, of which about 90% are spam. Typically between 50 and 60% of those spams are blocked without ever being delivered.
False positives are rather tough to guess because the vast majority of "false positives" are actually the spammers sending their spam out to their own e-mail address and clicking on a "this is not spam" button.
Ohh, and before anyone spouts out about how all the spam actually comes from AOL or Hotmail, there is actually virtually ZERO spam that really comes from either of these providers. What there is, is a LOT of spam that is send with the From: line listing either Hotmail or AOL (Yahoo, Lycos and Earthlink are other popular addresses). Many of these spams also falsify other headers to try to pretend that the message came through Hotmail or AOL.
Err, I think you must be confusing the "Tejas" and the "Banias" chip from Intel! The "Tejas" is going to be a desktop processor following in the Pentium 4 line. It will offer SIGNIFICANTLY higher performance than any Transmeta chip now or in the next 5+ years. However it will also consume a lot of power. Intel's current P4's are using nearly 100W of power at the high-end, and while the Prescott and Tejas will lower power consumption per-GHz, they will probably end up requiring even more power.
The "Banias", on the other hand, is Intel's low-powered notebook processor that will compete with Transmeta's line-up. As for how it will compare, it looks like it will use more power but offer WAY higher performance. The ULV 900MHz Banias chip is listed as consuming a maximum of 7W, which is very comperable to the maximum power of a 900MHz Crusoe TM5800. However, clock for clock, the PIII is usually twice as fast as the Crusoe, and the Banias will be faster still. Even Transmeta's next-generation of processors don't look like they'll offer much competition here. At best it looks like they might manage 70-80% of the clock-for-clock performance of the Banias.
I'm actually slightly dissapointed in the Banias specs though. From the first stories I heard about it, it sounded like all these chips would have a maximum power consumption in the 10-15W range, with the ULV chips consuming even less power. However, the 1.6GHz Banias has a maximum power consumption of almost 25W! To put things in perspective, only 5 or 6 years ago, 25-30W was considered to be a lot of power for a DESKTOP chip!
The reason to go for PCI is because ISA is shit! The ISA bus is quite possibly the worst bus ever designed, it was a terrible design 20+ years ago when it first came out and it didn't improve any with age. All modern systems now throw ISA onto the end of the PCI bus through a host-to-host bridge, but since ISA was designed so poorly, using an ISA device ends up using quite a bit more PCI bus bandwidth than the same device thrown on a PCI card. And after all that, you're still stuck with a device that can't share IRQs (due to the fact that interrupts on ISA are done in what is probably the worst possible way to do interrupts on a bus), can't be automatically configured with any sort of reliability (ISA Plug 'n Pray was extrodinarily unreliable in my experience).
Finally though, you can get WAY better sound quality out of a current sound card. Ok, this has absolutely nothing to do with the ISA vs. PCI vs. PCI Express deal, it's simply that the sound quality out of the SB16 isn't all that hot. I used to have one and thought that it sounded just fine. That is, until I bought an SBLive! to replace it and immediately noticed a world of difference in sound quality (on rather low-quality spearkers none the less!).
Anyway, long story short, I don't see any big reason to rush out and replace all PCI cards with PCI Express ones as soon as it comes out. But PLEASE, someone take the ISA bus out back and put it out of it's misery old-yeller style!
Err, they're using 1.2GHz AthlonXP-M processors. Those chips have a maximum power consumption of somewhere on the order of 25W, plus they have relatively advanced power saving features which can reduce power consumption dramatically when not going full-out. For comparison, Intel's P4-M processors at 1.6GHz use 30W of power or more and their "power saving" features (SpeedStep) is quite poor.
I'd actually guess that the main reason why Sun chose AMD over Intel is largely due to the heat issue and the fact that AMD's chips run cooler (despite what the uniformed masses at Slashdot might have us beleive:> )
This might have been Sun's selling point a while ago, but I think that this plan is starting to fall apart with just about every server processor moving quickly to 64-bits with the exception of Intel's Xeon line.
As for who will use AMD's x86-64 Opteron processors, I'd say that it actually makes most sense for Dell. Dell is now the only major server vendor that doesn't have their own processor. Sun has their Sparcs, IBM has their Power line, Fujitsu has their Sparc64 line, while HP essentially has the Itanium as their own processor.
Sure, Dell can buy Itanium's from Intel, but they end up with a the same processor that HP uses but lower quality chipsets and supporting architecture, and all 6+ months after HP gets their stuff. Any company selling Itanium based servers is going to be competing against HP at a serious disadvantage unless that company also puts the research and development money into developing their own chipsets and motherboards. IBM has made some motions in this direction, but research and development is definitaly NOT Dell's cup of tea.
Dell's strong point is slapping together systems that others have done almost all of the R&D for and most of the testing as well. Their strong point in servers is the Xeon market, and this is first and foremost where the Opteron is going to compete. What's more, a company called Newisys has made quite a bit of noise recently about their Opteron system designs. What this company proposes is to do all of the R&D work and most of the testing work in setting up Opteron servers and than selling these to big OEMs. The OEMs would than just need to slap all the parts together and sell them, ie right up Dell's alley.
Now, as for Sun, they're a bit of an odd case here. They're still kind of finding their feet in the x86 server world, so it's kind of tough to decide just where they're likely to go in the future. However, I would definitely guess that Opteron based x86-64 servers could offer them a reasonable solution for what they're after.
Err, HP is AMD's #1 customer! They certainly do sell AMD chips, and a lot of them! IBM also sells AMD chips, though currently not in any of their systems sold in North America. Still, they've been an on-again, off-again customer of AMD. Dell is the only major OEM that hasn't sold AMD chips, though ironically I'd say that they are the ones who would be best served by selling Opteron systems.
This sort of setup is theoretically possible, but EXTREMELY difficult to do in both the hardware and software involved. A similar setup has been done in the past with Macs which had an x86 chip in an add-in card to run x86 software. However, the bus used for a modern processor is MUCH more complicated and just wouldn't work at all in an add-in card (unless that add-in card was a whole PC in itself, and even then there would be a major bottleneck between the card and all I/O devices).
In short, while it's theoretically possible, don't expect to see it in any sort of production system. The cost of such a design would be MUCH higher than a traditional system, while performance would suffer as compared to a signle chip system running native software.
The main problem is that the theory sounds good, but the reality shows a LOT of problems. The Itanium is a VLIW processor, which is quite different from the more traditional RISC and CISC designs of other chips. The idea is rather similar to the difference between RISC and CISC (which, these days, are more or less the same thing), move more of the optimizations into the compiler to make the chip design more simple, thereby allowing more money to be spent on fatter pipes, bigger caches, etc. for the chip.
The problem though, is that it's often EXTREMELY difficult for compilers to effectively optimize software for VLIW chips. Since the Itanium has no out-of-order execution or branch prediction, these things have to be done entirely at compile time. The compiler needs to organize the software so that the chip is constantly being fed with data rather than having the chip dynamically rearrange some instructions if others are sitting waiting for data. It also needs to include it's own concept of branch prediction, suggesting which branch is more likely to occur. What's even worse (and which I rarely see mentioned) is that it has to optimize it's software for a particular chip design rather than an architecture, ie Itanium software needs to be recompiled for the Itanium2 in order to see many of the benefits of the new chip.
As far as manufacturing goes, that's comparatively easy for Intel at least. There they just have to put up with a huge die and extremely high power consumption. Not exactly a cheap chip to manufacturer, but manufacturing chips has always been Intel's specialty. Also, the high selling price of the Itanium means that Intel can afford quite a bit of leeway.
Anyway, long story short, the big problem with the Itanium/IA64 in general is that it's a design that is VERY difficult to optimize code for. It requires a very good compiler to begin with, but even then there are simpily some optimizations that just can't be done at compile time, and those situations will hurt the performance of the IA64 chips a lot. If Spec CPU2000 scores are anything to go by, the things from CINT (ie databases, compression, FPGA design, compilers, etc.) are much harder to optimize for IA64 than CFP (mostly scientific computing applications).
IA64 itself is not at all backwards compatible with IA32. The first Itanium processor had some sort of hardware-assisted IA32 emulation, but saying that it was really slow is an understatement. The 800MHz Itanium was generally about comperable to a Pentium 100 when it came to IA32 software.
After it was discovered just how terribly the Itanium was going to run IA32 software, Intel stopped talking about this capability altogether. From the looks of things, they've dropped the hardware emulation altogether from the Itanium2, though it may still exist as a (mostly?) undocumented feature.
Furthermore, no one disputes that the SDRAM patents that were at issue in this case were valid, and concerned technologies that Rambus actually did develop themselves.
Uhh, I'd say that a LOT of people would dispute at least some of the SDRAMs patents that Rambus has as being invalid! Unfortunately proving prior art on this sort of thing is VERY difficult, and proving that the patents cover something which is not "obvious" is harder still.
Still, whether it can be proven in a court or not, a lot of those patents are not entirely obvious, some are overly broad (ie they have some patents that could be used to cover just about any DDR bus, depending on interpretation). I remember reading about one of their patents that they claim cover SDRAM which involved storing timing information in a *register*! How the hell else would they store timing information?! Were they going to train a gerbil to sit inside the computer and tell the chips what the timings were supposed to be or something?! Of course they would use a register, that was a VERY obvious "innovation".
Rambus has done a LOT of immoral things with regards to their patents. This all started with the fact that way back in 1990, approximately 1 month after the company was formed, Rambus filed a patent that basically covered everything including the kitchen sink. This, of course, was determined to be overly broad, and wasn't granted, but the date of the original filling remaind. Then, over the next 8 years, Rambus developped their technologies and filed all their patents as extensions to their original patent. This is why you'll find a date of 1997 to 2000 on all of the SDRAM patents (SDRAM first started being produced in about 1995 if my memory serves me correctly), but they all are legally given a date of 1990 since they're all just extensions of the original Rambus patent. In short, they've done lots of things that are immoral, the question that the court is trying to answer is just how many of these things were illegal.
Two reasons. First, the "low powered" x86 chips are only low powered as compared to other x86 chips. Transmeta's Crusoe and VIA's C3/ESP chips both use somewhere on the order of 4-12W, depending on the speed grade. For comparison, AMD's Athlon's use anywhere from about 40-75W, while Intel's P4's can run even hotter at up to nearly 100W of power.
However, even 5W is quite high power consumption for this sort of chip. The IBM PowerPC 405LP in question uses a maximum of 500mW, so it's a whole order of magnitude less power than Transmeta and VIA. This is about the same power used by an Intel XScale or AMD Alchemy processor, two other competitors in the high-end embedded processor market.
The second reason for using this chip instead of an x86 chip, or even a regular PowerPC chip like the G4 is that the 405LP is a System-on-a-chip microcontroller rather than just a processor. In addition to the processor core, it also has a built-in SDRAM controller, video controller, I/O controller, etc.
This is actually the first time I've come across this particular chip, and I'm rather impressed. I've never really looked into IBM's embedded PowerPC chips, focusing more on ARM stuff as well as the low-end/el-cheapo embedded chips. I'm surprised we haven't seen more embedded Linux devices using these chips as opposed to ARM chips. It's only too bad that this chip doesn't seem to have an FPU. I'd really like to see a high-performance, low power embedded chip with an embedded floating point unit, but I guess that all that is a bit much to hope for at this moment in time.
Err, when exactly is it that IBM plans on making a "P4 killer"? The PowerPC 970, which is scheduled for release late this year is expected to manage a SpecInt score of 937, and a SpecFP score of 1051. By comparison, the Pentium4 at 3.06GHz, which is available NOW, scores 1085 and 1092 on SpecInt and SpecFP respectively.
In other words, that "P4 killer" that's on the way from IBM is going to be nearly a year behind the P4 in terms of performance.
As for IBM's 90nm fab process, how many 90nm chips do you see from IBM now? None. You know why? Because the 90nm process isn't finished yet! They've got the equipment, but they haven't actually started volume production of chips on that process yet, and probably won't for at least a few more months. I wouldn't count on being able to buy a chip produced on an 90nm IBM fab process before the end of the year, probably several months after you can buy a chip produced on an Intel 90nm fab process.
> The Itanium is unusable. Have you ever seen
> one production system with it? I have not.
I know somebody whose workplace (a research place of some sort) got a cluster of five hundred of them.
Ironically enough, that workplace owns roughly half of all Itanium processors that were ever actually sold! Ok, maybe it's not quite that bad anymore, but I remember the first sales reports for the Itanium said that they had sold just over 1000 processors, and of those, 500 had been sold to IBM to build a single cluster.
As for the cost, Itanium II systems are normally seen as relatively inexpensive solutions as compared to some of the stuff that Sun and IBM sell, though not by much. The real problem for Intel is Intel's own chips. A lot of what used to run on big Sun/IBM/HP servers running commercial Unix is now being run on low-cost Intel Xeon servers running Windows, Linux, FreeBSD, etc.
I'd tend to disagree with you here. When it comes to raw computational power, the Itanium II is easily matching the best that Sparc and MIPS chips out there in integer, and it's absolutley mopping the floor with them when it comes to floating point power. Only the almost-non-existant Alpha EV7 from HPaq and IBM's Power4 are in the running here. And of course Intel's own Pentium4.
Where MIPS and Sparc really excell is not in their processing power, but in their I/O abilities, processor interconnects, etc. So, by delaying the release of a dual-core chip (which would mainly just improve it's number crunching ability, but do nothing for I/O), Intel isn't likely to be losing out much.
Of course, the real thing that's holding the Itanium back now isn't so much with the hardware at all, but rather with the software, which is quite immature and doesn't seem to be advancing nearly as fast as Intel and HP had hoped.
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I've been working in the spam-fighting industry (sad that this actually is an industry now!) for a few months now, and that's the one question that's been bothering me.
My conclusion: It's NOT profitable!
Sure, there are the few people who SEND spam that make lots of money, but by and large, the people actually trying to sell stuff by spam are losing money.
Everyone always talks about how cheap it is to send tons of spam, but cheap or not, it still costs SOME amount of money. The big spammers spend thousands of dollars a month (or more) just for their internet connections, while the small-time spammers sending from their DSL connections can only get out, at best, about 100,000 messages before their connection is killed.
But despite that, there is a LOT of spam, a REALLY large quantity of it. I did some rough estimates and figured that there is at least 10 billion spam messages being sent each and every day (Hotmail alone receives roughly 2 billion spam messages a day). Even at a cost of only $10/million messages (and I'd wager that the costs I've seen are at least 10 times that much), we're talking about spammers spending hundreds of thousands of dollars a day!
Now, some of this might be profitable, particularly some of the porn spam, the ones that really get me though are the thing like all the penis enlargement spam. These so-called "penile-enhancement" pills make up probably 5-10% of all spam. I'd figure at a minimum spammers are spending $10,000 a day sending out penis enlargement spam. Now, I realize that PT Barnum told us that there are suckers born every minute, but there honestly are just not that many complete and utter morons born every second to make this sort of thing possible!
The real trick though is that some companies have made a lot of money selling spam. They've managed to convice the suckers that are born every minute that simply sending out penis-enlargement spam ads to millions of people will make them money. End result, the people actually trying to sell stuff by spam are losing money by the boatload, but there are are just too many dumbasses on the planet! Even after thousands have lost money sending this spam before them, people are still lining up to be the next one to send you a penis enlargement spam because they're absolutely certain that they'll exploit the "dumb masses" and make tons of money.
FWIW Cyrix is dead in all but the name, and even that is pretty much gone. Cyrix as a seperate entity disapeared some time ago when they were bought by National Semi. NS then proceeded to mismange, bungle and thwart all attampts to do anything useful for the next two+ years, before finally giving up and selling the Cyrix MII processor, the Cyrix name and most Cyrix employees to VIA. NS kept the MediaGX chip to themselves, and still sell it, albeit it in virtually non-existant quantities.
As for VIA, they sold the MII for a short time, but that was the ONLY Cyrix chip they ever sold, and it didn't last that long. They basically sacked the entire Cyrix development teams and have now dropped the Cyrix name as well in favor of the names like "VIA C3". As for the chips, these are actually designed by the old IDT/Centaur "Winchip" design team, which VIA bought at almost the same time as their Cyrix purchase.
That'sa reasonably good point, though I don't anticipate Transmeta making too much of a dent here any time soon. The higher bandwidth memory and Hypertransport bus on the new Astro migh help, but they really need to get the performance of the chip up to half-way respectable levels first.
However, the Pentium-M looks like a KICK-ASS blade server processor to me! Beyond the low power consumption, it has 1MB of L2 cache! What's more, it's got a 400MHz bus, which should help for some decent I/O performance. Combine that with a fairly powerful CPU core, and you've got quite a very nice solution.
How much would you pay to get rid of the noise your computer makes?
Not much, fortunately. VIA's C3 processors consume roughly the same amount of power that the Transmeta chips consume, they sell for a fraction of the price, they are reasonably easy to find, they work on TONS of motherboards (most modern P3 boards), and to top it off, they beat the pants off anything Transmeta's put out when it comes to performance (which isn't saying much).
Yup, the systems will be NUMA. However, AMD is trying to coin a new phrase for their chips, SUMO (Sufficiently Uniform Memory Organisation, I think). They even have a little drawing of a sumo wrestler on some of their documents :>
The idea is that they will use their Hyptertransport links as a high-speed, cache-coherant, memory bus. Their claim is that the interconnect links will have enough bandwidth and sufficiently low latency that you can completley ignore the fact that it's a NUMA system and treat it exactly the same as a UMA system.
In reality, the chips will probably benefit from some NUMA optimizations, however the setup does look pretty good. Typically accessing remote memory will still be just as fast as accessing memory through an external memory controller, as is done in all current x86 systems.
That's actually a very good question, since the rumors as to the difference seem to change about every second day!
Originally there were two chips, the Sledgehammer and the Clawhammer. The Sledge had 1MB of L2 cache, 3 Hypertransport links and a 128-bit wide memory controller. The Clawhammer had 256KB of L2 cache, 1 Hypertransport link and a 64-bit wide memory controller.
At first it seemed like the Sledgehammer was just going to get the official name of "Opteron" while the Clawhammer would get the official name of "Athlon64". However, it no longer seems that simple, since there are THREE different versions of the Opteron (the 100, 200 and 800 series models). What's more, it's looking like AMD might shy away from using only 256K of cache on their desktop chip since Intel will just be releasing new desktop chips with 1MB of cache at the same time.
So, where does that leave us? Well, I dunno for sure, but this is my guess:
Opteron 100 series: 1MB of cache, 1 Hypertransport link, 128-bit wide memory bus, only for single processor systems
Opteron 200 series: 1MB of cache, 2 Hypertransport links, 128-bit wide memory bus, for dual-processor systems
Opteron 800 series: 1MB of cache, 3 Hypertransport links, 128-bit wide memory bus, for up to 8-way SMP systems
Athlon64: 1MB of cache, 1 Hypertransport link, 64-bit wide memory bus, only for single processor systems
"Athlon64-Lite" (Duron64?): 256KB of cache, 1 HT link, 64-bit memory bus, single-processor only.
Of course, it could be a bit trickier than that. Also, I've seen documents from AMD where their "single" 16-bit Hypertransport link could be split into two 8-bit HT links and allow for dual-processor operation. So, perhaps the Opteron 100 and Opteron 200 series will be identical except that the latter will be certified for use in dual-processor systems? If this is the case, than the Athlon64 would also (at least theoretically) work in dual-processor systems.
It's also quite possible that AMD will have one or more processor with 512K of cache, rather than the 256K or 1MB originally planned.
Long story short, until AMD announced the official specs, no one really knows for sure.
No, the pointers are still 64-bits, it's just that the top ~20 of those bits will be rather useless for the time being (the Opteron supports 40-bit physical addresses, but something like 45 virtual address lines). The previous poster was correct, the idea behind this was that the number of pins for the address bus.
To answer the previous poster's question, yes, the chip can be expanded to right up to the full 64-bits of physical address space without any changes to the ISA.
AMD's Opteron processor will be offered in three varieties:
Opteron 1xx series - Single processor workstations/servers
Opteron 2xx series - Dual processor workstations/server
Opteron 8xx series - Up to 8-way SMP servers
The first two are pretty directly targeting the market that the Xeons currently sell into, but the last one starts to touch on the Itanium's market. The Xeon tends not to scale well beyond 2 processors, and in fact, most Xeons won't work at all in anything more than 2-way systems (only the Xeon MP is certified for use in 4+ processor systems).
As for price, AMD hasn't announce any prices, but I think it's quite reasonable to assume that the 1xx series of Opterons will be quite reasonably priced (probably not significantly more than an AthlonXP or P4), the 2xx series will be priced similar to the Xeon (about 10-20% more than a P4 of the same clock rate), while the 8xx chips will cost about the same as a Xeon MP ($1000-$2000).
Of course, when it comes to servers, the processor is only one relatively small part of the equation, and so far all the Opteron servers I've seen have been pretty high-end systems, so I don't expect them to be cheap.
In a word, no.
First off, every x86 chip since the original Penium have used 64-bit buses anyway! ie they reversed the old 386SX, using 32-bits internally, but 64-bits externally.
The next problem in your theory is that the Hammer completely changes all the rules about buses anyway (at least the x86-rules of buses). The processor will have an on-die memory controller, which basically eliminates most of the traffic that went over a traditional bus. In current x86 systems, there is only one bus that transports both the memory data and I/O data. In Hammer systems, there will be two or more buses, one for memory and 1 to 3 of them for all other I/O. Ironically, these I/O buses will be reduced down to 16-bits, though they run at quite high speeds and offer comperable bandwidth to today's 64-bit buses (this is what AMD calls Hypertransport).
The most important reason though is simply that motherboards are dirt-cheap these days, and demand for upgrade chips is such a tiny market that it's totally trivial and can be very easily ignored (which is sometimes kind of annoying for the odd-balls like myself who might actually buy such a product!)
Obviously you didn't bother reading the article before posting did you? I guess I shouldn't expect that though.
While it is true that 32-bit x86 chips can address 36-bits of memory using Intel's PAE, they do so using a really ugly hack. It was a really ugly hack back in the 16-bit x86 days, and it's still an ugly hack now.
AMD's solution is the right one, a true flat 64-bit address space. 64-bit integers aren't particularly important, it's quite rare that an application needs 64-bit integers, and when they do they can easily be handled with two 32-bit integers (albeit at a significantly reduction in performance as compared to true 64-bit integers). 64-bit addressing is what x86 is all about. Well, that and clearing up a few of the remaining problem spots in x86, ie doubling the registers and getting rid of some mostly-useless modes.
It's 40% by the number of messages, and you're definitely right about spam messages being, on average, much larger than non-spam messages. At a rough guess, I'd say that by % of total size, spam would make up somewhere around 70-80% of all e-mail traffic.
FWIW the 40% number is probably a reasonably good cross-section of ALL internet e-mail sent (it wouldn't count internal company e-mail). Presumably it takes into account all of Brightmail's customers. A lot of Brightmail's customer's are corporations blocking their company mail, which have much lower levels of spam than personal e-mail accounts. However Brightmail also has a LOT of major ISPs using their filtering software, eg MSN / Hotmail, AT&T WorldNet, Earthlink, etc. These customers see much higher percentages of spam.
Just as a FWIW, I know for a fact that Hotmail regularly blocks over a billion spam messages a day, though exact numbers are slightly tough to compare since Hotmail counts their messages differently than AOL does (1 message to 100 address = 1 message for Hotmail vs. 100 messages for AOL as I understand it). In total, Hotmail gets about 2.3 billion messages a day, of which about 90% are spam. Typically between 50 and 60% of those spams are blocked without ever being delivered.
False positives are rather tough to guess because the vast majority of "false positives" are actually the spammers sending their spam out to their own e-mail address and clicking on a "this is not spam" button.
Ohh, and before anyone spouts out about how all the spam actually comes from AOL or Hotmail, there is actually virtually ZERO spam that really comes from either of these providers. What there is, is a LOT of spam that is send with the From: line listing either Hotmail or AOL (Yahoo, Lycos and Earthlink are other popular addresses). Many of these spams also falsify other headers to try to pretend that the message came through Hotmail or AOL.
Err, I think you must be confusing the "Tejas" and the "Banias" chip from Intel! The "Tejas" is going to be a desktop processor following in the Pentium 4 line. It will offer SIGNIFICANTLY higher performance than any Transmeta chip now or in the next 5+ years. However it will also consume a lot of power. Intel's current P4's are using nearly 100W of power at the high-end, and while the Prescott and Tejas will lower power consumption per-GHz, they will probably end up requiring even more power.
The "Banias", on the other hand, is Intel's low-powered notebook processor that will compete with Transmeta's line-up. As for how it will compare, it looks like it will use more power but offer WAY higher performance. The ULV 900MHz Banias chip is listed as consuming a maximum of 7W, which is very comperable to the maximum power of a 900MHz Crusoe TM5800. However, clock for clock, the PIII is usually twice as fast as the Crusoe, and the Banias will be faster still. Even Transmeta's next-generation of processors don't look like they'll offer much competition here. At best it looks like they might manage 70-80% of the clock-for-clock performance of the Banias.
I'm actually slightly dissapointed in the Banias specs though. From the first stories I heard about it, it sounded like all these chips would have a maximum power consumption in the 10-15W range, with the ULV chips consuming even less power. However, the 1.6GHz Banias has a maximum power consumption of almost 25W! To put things in perspective, only 5 or 6 years ago, 25-30W was considered to be a lot of power for a DESKTOP chip!
The reason to go for PCI is because ISA is shit! The ISA bus is quite possibly the worst bus ever designed, it was a terrible design 20+ years ago when it first came out and it didn't improve any with age. All modern systems now throw ISA onto the end of the PCI bus through a host-to-host bridge, but since ISA was designed so poorly, using an ISA device ends up using quite a bit more PCI bus bandwidth than the same device thrown on a PCI card. And after all that, you're still stuck with a device that can't share IRQs (due to the fact that interrupts on ISA are done in what is probably the worst possible way to do interrupts on a bus), can't be automatically configured with any sort of reliability (ISA Plug 'n Pray was extrodinarily unreliable in my experience).
Finally though, you can get WAY better sound quality out of a current sound card. Ok, this has absolutely nothing to do with the ISA vs. PCI vs. PCI Express deal, it's simply that the sound quality out of the SB16 isn't all that hot. I used to have one and thought that it sounded just fine. That is, until I bought an SBLive! to replace it and immediately noticed a world of difference in sound quality (on rather low-quality spearkers none the less!).
Anyway, long story short, I don't see any big reason to rush out and replace all PCI cards with PCI Express ones as soon as it comes out. But PLEASE, someone take the ISA bus out back and put it out of it's misery old-yeller style!
Err, they're using 1.2GHz AthlonXP-M processors. Those chips have a maximum power consumption of somewhere on the order of 25W, plus they have relatively advanced power saving features which can reduce power consumption dramatically when not going full-out. For comparison, Intel's P4-M processors at 1.6GHz use 30W of power or more and their "power saving" features (SpeedStep) is quite poor.
:> )
I'd actually guess that the main reason why Sun chose AMD over Intel is largely due to the heat issue and the fact that AMD's chips run cooler (despite what the uniformed masses at Slashdot might have us beleive
This might have been Sun's selling point a while ago, but I think that this plan is starting to fall apart with just about every server processor moving quickly to 64-bits with the exception of Intel's Xeon line.
As for who will use AMD's x86-64 Opteron processors, I'd say that it actually makes most sense for Dell. Dell is now the only major server vendor that doesn't have their own processor. Sun has their Sparcs, IBM has their Power line, Fujitsu has their Sparc64 line, while HP essentially has the Itanium as their own processor.
Sure, Dell can buy Itanium's from Intel, but they end up with a the same processor that HP uses but lower quality chipsets and supporting architecture, and all 6+ months after HP gets their stuff. Any company selling Itanium based servers is going to be competing against HP at a serious disadvantage unless that company also puts the research and development money into developing their own chipsets and motherboards. IBM has made some motions in this direction, but research and development is definitaly NOT Dell's cup of tea.
Dell's strong point is slapping together systems that others have done almost all of the R&D for and most of the testing as well. Their strong point in servers is the Xeon market, and this is first and foremost where the Opteron is going to compete. What's more, a company called Newisys has made quite a bit of noise recently about their Opteron system designs. What this company proposes is to do all of the R&D work and most of the testing work in setting up Opteron servers and than selling these to big OEMs. The OEMs would than just need to slap all the parts together and sell them, ie right up Dell's alley.
Now, as for Sun, they're a bit of an odd case here. They're still kind of finding their feet in the x86 server world, so it's kind of tough to decide just where they're likely to go in the future. However, I would definitely guess that Opteron based x86-64 servers could offer them a reasonable solution for what they're after.
Err, HP is AMD's #1 customer! They certainly do sell AMD chips, and a lot of them! IBM also sells AMD chips, though currently not in any of their systems sold in North America. Still, they've been an on-again, off-again customer of AMD. Dell is the only major OEM that hasn't sold AMD chips, though ironically I'd say that they are the ones who would be best served by selling Opteron systems.
This sort of setup is theoretically possible, but EXTREMELY difficult to do in both the hardware and software involved. A similar setup has been done in the past with Macs which had an x86 chip in an add-in card to run x86 software. However, the bus used for a modern processor is MUCH more complicated and just wouldn't work at all in an add-in card (unless that add-in card was a whole PC in itself, and even then there would be a major bottleneck between the card and all I/O devices).
In short, while it's theoretically possible, don't expect to see it in any sort of production system. The cost of such a design would be MUCH higher than a traditional system, while performance would suffer as compared to a signle chip system running native software.
The main problem is that the theory sounds good, but the reality shows a LOT of problems. The Itanium is a VLIW processor, which is quite different from the more traditional RISC and CISC designs of other chips. The idea is rather similar to the difference between RISC and CISC (which, these days, are more or less the same thing), move more of the optimizations into the compiler to make the chip design more simple, thereby allowing more money to be spent on fatter pipes, bigger caches, etc. for the chip.
The problem though, is that it's often EXTREMELY difficult for compilers to effectively optimize software for VLIW chips. Since the Itanium has no out-of-order execution or branch prediction, these things have to be done entirely at compile time. The compiler needs to organize the software so that the chip is constantly being fed with data rather than having the chip dynamically rearrange some instructions if others are sitting waiting for data. It also needs to include it's own concept of branch prediction, suggesting which branch is more likely to occur. What's even worse (and which I rarely see mentioned) is that it has to optimize it's software for a particular chip design rather than an architecture, ie Itanium software needs to be recompiled for the Itanium2 in order to see many of the benefits of the new chip.
As far as manufacturing goes, that's comparatively easy for Intel at least. There they just have to put up with a huge die and extremely high power consumption. Not exactly a cheap chip to manufacturer, but manufacturing chips has always been Intel's specialty. Also, the high selling price of the Itanium means that Intel can afford quite a bit of leeway.
Anyway, long story short, the big problem with the Itanium/IA64 in general is that it's a design that is VERY difficult to optimize code for. It requires a very good compiler to begin with, but even then there are simpily some optimizations that just can't be done at compile time, and those situations will hurt the performance of the IA64 chips a lot. If Spec CPU2000 scores are anything to go by, the things from CINT (ie databases, compression, FPGA design, compilers, etc.) are much harder to optimize for IA64 than CFP (mostly scientific computing applications).
IA64 itself is not at all backwards compatible with IA32. The first Itanium processor had some sort of hardware-assisted IA32 emulation, but saying that it was really slow is an understatement. The 800MHz Itanium was generally about comperable to a Pentium 100 when it came to IA32 software.
After it was discovered just how terribly the Itanium was going to run IA32 software, Intel stopped talking about this capability altogether. From the looks of things, they've dropped the hardware emulation altogether from the Itanium2, though it may still exist as a (mostly?) undocumented feature.
Furthermore, no one disputes that the SDRAM patents that were at issue in this case were valid, and concerned technologies that Rambus actually did develop themselves.
Uhh, I'd say that a LOT of people would dispute at least some of the SDRAMs patents that Rambus has as being invalid! Unfortunately proving prior art on this sort of thing is VERY difficult, and proving that the patents cover something which is not "obvious" is harder still.
Still, whether it can be proven in a court or not, a lot of those patents are not entirely obvious, some are overly broad (ie they have some patents that could be used to cover just about any DDR bus, depending on interpretation). I remember reading about one of their patents that they claim cover SDRAM which involved storing timing information in a *register*! How the hell else would they store timing information?! Were they going to train a gerbil to sit inside the computer and tell the chips what the timings were supposed to be or something?! Of course they would use a register, that was a VERY obvious "innovation".
Rambus has done a LOT of immoral things with regards to their patents. This all started with the fact that way back in 1990, approximately 1 month after the company was formed, Rambus filed a patent that basically covered everything including the kitchen sink. This, of course, was determined to be overly broad, and wasn't granted, but the date of the original filling remaind. Then, over the next 8 years, Rambus developped their technologies and filed all their patents as extensions to their original patent. This is why you'll find a date of 1997 to 2000 on all of the SDRAM patents (SDRAM first started being produced in about 1995 if my memory serves me correctly), but they all are legally given a date of 1990 since they're all just extensions of the original Rambus patent. In short, they've done lots of things that are immoral, the question that the court is trying to answer is just how many of these things were illegal.
Two reasons. First, the "low powered" x86 chips are only low powered as compared to other x86 chips. Transmeta's Crusoe and VIA's C3/ESP chips both use somewhere on the order of 4-12W, depending on the speed grade. For comparison, AMD's Athlon's use anywhere from about 40-75W, while Intel's P4's can run even hotter at up to nearly 100W of power.
However, even 5W is quite high power consumption for this sort of chip. The IBM PowerPC 405LP in question uses a maximum of 500mW, so it's a whole order of magnitude less power than Transmeta and VIA. This is about the same power used by an Intel XScale or AMD Alchemy processor, two other competitors in the high-end embedded processor market.
The second reason for using this chip instead of an x86 chip, or even a regular PowerPC chip like the G4 is that the 405LP is a System-on-a-chip microcontroller rather than just a processor. In addition to the processor core, it also has a built-in SDRAM controller, video controller, I/O controller, etc.
This is actually the first time I've come across this particular chip, and I'm rather impressed. I've never really looked into IBM's embedded PowerPC chips, focusing more on ARM stuff as well as the low-end/el-cheapo embedded chips. I'm surprised we haven't seen more embedded Linux devices using these chips as opposed to ARM chips. It's only too bad that this chip doesn't seem to have an FPU. I'd really like to see a high-performance, low power embedded chip with an embedded floating point unit, but I guess that all that is a bit much to hope for at this moment in time.
Err, when exactly is it that IBM plans on making a "P4 killer"? The PowerPC 970, which is scheduled for release late this year is expected to manage a SpecInt score of 937, and a SpecFP score of 1051. By comparison, the Pentium4 at 3.06GHz, which is available NOW, scores 1085 and 1092 on SpecInt and SpecFP respectively.
In other words, that "P4 killer" that's on the way from IBM is going to be nearly a year behind the P4 in terms of performance.
As for IBM's 90nm fab process, how many 90nm chips do you see from IBM now? None. You know why? Because the 90nm process isn't finished yet! They've got the equipment, but they haven't actually started volume production of chips on that process yet, and probably won't for at least a few more months. I wouldn't count on being able to buy a chip produced on an 90nm IBM fab process before the end of the year, probably several months after you can buy a chip produced on an Intel 90nm fab process.
> The Itanium is unusable. Have you ever seen > one production system with it? I have not.
I know somebody whose workplace (a research place of some sort) got a cluster of five hundred of them.
Ironically enough, that workplace owns roughly half of all Itanium processors that were ever actually sold! Ok, maybe it's not quite that bad anymore, but I remember the first sales reports for the Itanium said that they had sold just over 1000 processors, and of those, 500 had been sold to IBM to build a single cluster.
As for the cost, Itanium II systems are normally seen as relatively inexpensive solutions as compared to some of the stuff that Sun and IBM sell, though not by much. The real problem for Intel is Intel's own chips. A lot of what used to run on big Sun/IBM/HP servers running commercial Unix is now being run on low-cost Intel Xeon servers running Windows, Linux, FreeBSD, etc.
I'd tend to disagree with you here. When it comes to raw computational power, the Itanium II is easily matching the best that Sparc and MIPS chips out there in integer, and it's absolutley mopping the floor with them when it comes to floating point power. Only the almost-non-existant Alpha EV7 from HPaq and IBM's Power4 are in the running here. And of course Intel's own Pentium4.
Where MIPS and Sparc really excell is not in their processing power, but in their I/O abilities, processor interconnects, etc. So, by delaying the release of a dual-core chip (which would mainly just improve it's number crunching ability, but do nothing for I/O), Intel isn't likely to be losing out much.
Of course, the real thing that's holding the Itanium back now isn't so much with the hardware at all, but rather with the software, which is quite immature and doesn't seem to be advancing nearly as fast as Intel and HP had hoped.