Both the terms "front side bus" and "northbridge" are rather outdated and really don't apply to the Hammer architecture at all.
"Front Side Bus" stemmed from the PPro, which had two memory data buses, one on the "front side", which connected to the memory controller and everything else, and one on the "back side" which connected to the cache. With the Hammer, the cache is integrated so the "back side" bus never leaves the die (same as with the P4 and the AthlonXP) while the memory controller is also integrated, so part of it's "front side" never leaves the chip either, it just has a memory bus. Hypertransport is a chip-to-chip interconnect that is used for the rest of the system. You can call it a "front side bus" if you like, though the term really doesn't make any sense in this context.
"Northbridge" and "southbridge" also no longer make any sense. These terms originated because they were the "north" and the "south" end of a PCI bridge, which gave the processor a way to talk to PCI devices. Of course, the functions that these chips now perform no longer have any PCI at all in them, and the bridge is entirely in the I/O chip (what some people are still calling the "south bridge"). Intel is using their Accelerated Hub Architecture instead of PCI for interconnects, while AMD will be moving to using Hypertransport again as a chip-to-chip interconnect. AMD calls their chips "hypertransport tunnels", which is a somewhat more accurate title then a PCI bridge.
FWIW the only chipsets that I'm aware of which still use actual PCI north and south bridges are the AMD 760MP(X) and the ATI Radeon chipsets. AMD uses 66MHz/64-bit PCI to interconnect their chipsets, which gives them as much bandwidth as any competing technologies. ATI, meanwhile, is using 32-bit/33MHz, which is part of the reason why their Radeon chipset will likely really stink in the desktop market (nice for laptops, useless for desktops.. but I digress)
YOu think that's funny, I think I lived in the guy's house last year!
I guess he now lives/teaches down in the states somewhere, but still own a house in Canada where he lives, and during the school year he rents it outto students such as myself!
Great prof he may be, but not a very great landlord!:>
I'm not aware of any commercial MP3 decoders for Linux, at all.
Actually, Winamp released a really early alpha version of Winamp 3.0 for Linux a little while back. I remember using it, and it was TERRIBLE, barely able to play a single song without crashing, but this was at a time when the Windows version of WinAmp 3.0 wasn't particularly stable either.
Winamp does say on their web page in their FAQ that "Support for Linux and other UNIX flavors is in the works." I haven't seen it yet and it would seem that it's been moved to the back-burner, but at least it would seem that it's still on the stove-top.
I think any consparicy theory can stay within Fraunhofer itself. This same organisation is pushing to make MP3Pro as the next standard, and that too would have a licensing fee associated with it. Maybe they're just trying to level the playing field, so to speak, by charging a fee for licensing for MP3 players, while MS and RP also have some sort of licensing for their own audio format. Then hope that their well recognized "mp3" name will carry them over to the next round and their MP3Pro will win out over MS and Real.
Of course, Ogg Vorbis is the real wildcard in the deck, and that could ruin the plans of all three companies. Ogg offers quality that matches or beats the others at absolutely no cost and with no restrictions. If enough Joe-users start to know about the situation, Ogg may quickly become the dominant standard.
Yes, they most definitely are. The exact nature of the licensing agreement varies somewhat for this software, though in general it is a lot MORE restrictive then the license for MPEG1 (video or audio). Actually, that's a large part of the reason why MP3 audio (mpeg1) became so popular even though at that time mpeg2 audio was already available and a well known quantity. Mpeg1 was cheap/free while mpeg2 was expensive.
AMD never licensed Slot 1, what they did is they "developed" a new slot that was physically identical but flipped around backwards. They called it Slot A.
AMD could NOT use the same motherboard, regarldess of the slot use. The connector was actually of no consequence at all, it was all in the bus protocol used, which Intel would NOT license to AMD at all.
As for Cyrix, they never had a license either, they just used the P3 socket all on their own. They claimed (and still are claiming) that a cross-licensing agreement through their various owners allows them to make use of the GTL+ bus protocol that was used with the PPro, PII and PIII.
Above and beyond what the original poster wrote, take a look sometime at the "errata" or "specification update" sheets that both Intel and AMD document.
These errata sheets describe all the ways in which various processors are not compatible with the IA-32 specification. Last I checked, the P4 had 50-60 documentated incompatabilities, while the PIII had over 80. These are specifically documented situations where Intel is NOT "Intel compatible". The Athlon, meanwhile, had about 15-20.
I'll leave it as an exercise to the reader to figure out if AMD is actually MORE Intel compatible than Intel is, or if Intel just documents their incompatabilities better then AMD.
Ohh, as for point 2 above, the issue was not so much one of Intel patenting Slot 1. AMD's first Athlons used a "Slot A", which was actually just a Slot 1 connector flipped backwards. The real issue though was that Intel had patented the GTL+ bus used for PPro, PII and PIII processors. Part of the legal agreement between AMD and Intel after the 386 and 486 battle was that AMD was NOT allowed to use any Intel bus designs beyond the Pentium bus. The socket/slot used by Intel was immaterial, it was the bus protocol that AMD could not use.
Don't underestimate the potentially detrimental performance impact of the rather small L1 data cache of the P4. Something like 1 out of every 3 instructions in x86 code is a load or store, so even a relatively small difference in cache hit rates can make a BIG difference in performance. This is a large part of the reason why the P4 benefits so much from going from 256K to 512K of L2 cache, it needs it's L2 hit rate as high as possible to offset the relatively low L1 hit rate.
Just what is the exact difference in hit rates between the P4's 8K of L1 data and teh Athlons 64K L1 data cache (the other 64K is an instruction cache, more on that later)? Well that depends entirely on your application. Most numbers I've seen would tend to indicate that your 5% number isn't too far off for most applications though. However, that 5% turns into a VERY large performance difference. Even the fastest L2 cache (ie that which is used in the P4) has a 7-10 cycle latency, and main memory latency is up around 250-300 cycles these days.
The Athlon also has another slight cache advantage, in that it's cache is dual-ported, while to the best of my knowledge, the cache of the P4 is not. That means that the Athlon can be doing loads and stores at the same time, while the P4 can't. This helps the Athlon avoid some real-world latency that might not show up in the theoretical latency numbers.
Ohh, as for the total cache sizes, it's really only valid to compare 8K for teh P4 to 64K for the Athlon. The Athlon has a 64K data and 64K instruction cache. The P4 has a 8K data cache but a 12K micro-op trace cache instead of instruction cache. The trace cache, IMO, is the best/most innovative part of teh entire P4 design, as it stores already-decoded instructions in the cache rather then the x86 instructions. The end result is that this about equivalent to a 20-22K L1 instruction cache, except faster.
Anyway, long story short, I think that the P4's trace cache is great, but it's data cache is too small IMO. It allows Intel to clock the chip to very high speeds, while still keeping the memory latency low, but it makes the chip VERY dependent on the L2 cache and memory subsystem. Memory latency is HUGE these days (for comparison sake, the 386 had a memory latency of 1 clock cycle, today we have a memory latency of about 250-300 clock cycles), and with the P4's high clock speed but long pipeline, any sort of pipe stalls are a VERY bad thing for performance. Even stalling to get data from the L2 cache can be somewhat bad for the P4.
Actaully AMD had the performance lead for longer then that. They took the performance crown away from Intel the day that the Athlon was first released, since it came out at 650MHz when the fastest PIII was only 600MHz, and the Athlon was, at that time, just slightly faster clock for clock then the PIII. AMD kept the clock speed lead and increased their clock-for-clock performance over the PIII up for the next few years. Intel only just started to catch up with the P4 2.0GHz (which was released just a little bit before the AthlonXP, ie when the fastest Athlon was only at 1.4GHz).
Basically for the last 3 years (since the release of the Athlon), AMD has had the fastest x86 chips for about 2 years. Intel has had the fastest x86 chips for about 6 months, and for the remaining 6 months it's been too close to tell which was faster.
As for the P4s long pipeline, I'd say that it WAS largely responsible for increasing the performance because it allowed Intel to clock the chips so damn high. They clocked the P4 up to 2.0GHz easily on a 180nm fab process. Compare this to the PIII which they struggled to get up to 1.13GHz on the exact same 180nm process (and that took them until 1 year after their first attempt failed miserably and had to be recalled completely). AMD did slightly better with their Athlon design, but it still was only able to clock up to 1.73GHz on a 180nm process, and they had a more advanced process then Intel did in some ways (ie they were using copper interconnects).
Long story short, performance is determined (in an overly simplified way) by IPC * clock speed. With the P4, Intel looked to sacrafice IPC slightly to dramatically increase the clock speed with the goal of overall faster performance. When compared to the PIII at least, they definitely succeeded. Compare the fastest 180nm process PIII (1.13GHz) to the fastest 180nm process P4 (2.0GHz) and which do you think is faster?
FWIW, last I checked, Van actually works for VIA, in the division that designs the VIA/Cyrix processors (ie the people that VIA bought from IDT when they acquired the IDT Centaur Winchip design team).
He's no fan of Intel, though I don't know that he's exactly AMD's bitch either.
SPEC CFP2000 is by far the most widely supported benchmark, but it has it's share of flaws, just look at Sun's latest SPEC CFP2000 scores and you might notice one of them. For the Sun Blade 1900 (900MHz USIII), Sun had a rather abysmal CFP score, with the Sun Blade 1900 Cu (900MHz USIII), they were suddenly quite competative. Hugely improved compiler right?! Wrong. Actually they only improved by 0-15% on most benchmarks (about what could be expected with a slightly better compiler, ie what you could expect in the real world), however their CFP score improved by over 50%. Why is that? Well ONE single sub-bench of CFP (179.art) was increased by a remakable 560%! The end result is that the USIII looks like a rather fast chip at floating point, when it's actually butt-slow (WAY slower then either the Athlon or the P4) at everything except for one particular Fortran application. This isn't to say that Sun's score is invalid, simply that it doesn't take much to really skew the scores of ANY benchmark, including SPEC CFP.
I've also critized SPEC in the past for being a bit to focused on large datasets. For example, the 171.swim benchmark is essentially a memory bandwidth test taken from some shallow water modeling code. Now, that isn't to say that memory bandwidth isn't important for floating point and scientific applications (if it weren't IBM wouldn't have thrown a whole boatload of bandwidth at their Power4), simply that SPEC seems to have over-emphasized this aspect. I think the reason for this is that SPEC CPU95 was just the opposite, and often critized for emphasizing SMALL datasets too much, and therefore become almost completely a test of the cache architecture of the processor in many cases. For CPU2000, it seems like they over-corrected in my mind.
Long story short, if your floating point work involves small datasets, the Athlons MUCH larger L1 cache and 3 floating point execution units will crunch the code much faster. On large datasets, the P4's higher bus and memory bandwidth and larger L2 cache will crunch the code faster.
You're quite correct in that saying that the P4 has a weak FPU is definitely wrong. The chip actually is VERY good at floating point calculations, better then just about anything out there. Only the Power4 and the Itanium2 are decidely faster FP number crunchers then the P4.
Over 80% of new PCs sold next year might contain P4-based cores. At the moment it's only slightly over 50% of all new PCs sold (the Athlon sells up around 20%, the PIII still gets a fair number of sales (10%?), and Celeron chips based on the PIII core are still quite common as well (20%?).
Still, when compared to the total number of PCs out there, the ~200 million P4-based PCs that will be on the market by the end of next year isn't all that big of a number. There are still a LOT of people out there using PIII, PII and Pentium systems, as well as their Celeron derivatives of such chips, not to mention all the Athlons and K6s, as well as the Hammer chips that will be out next year as well.
Long story short, there are a LOT of x86 architectures out there, and they ALL have different optimizations requirements. Since virtually no one hand tunes their own applications for a specific chip (which would require getting down to the assembly level for the most part), it's up to the compilers to optimize for a specific chip, and generally speaking, it's a LOT more effective and a lot easier to just do general optimizations rather then core-specific optimizations. General optimizations will benefit ALL the x86 chips out there, while core-specific optimizations will only benefit a small proportion of the chips for any given time frame, after which point a new chip will come out to replace that core.
Memory throughput numbers are LARGELY determined by the bandwidth of the processor bus. AMD has 2.1GB/s of processor bus bandwidth (133/266MHz DDR, 64-bits wide), while Intel has 3.2GB/s or 4.2GB/s (100/400MHz or 133/533MHz QDR, 64-bits wide). This is the reason why Intel processors score higher on memory bandwidth tests, not VIA.
Note: don't expect a review on Tom's Hardware to pick up on something like this, you have to actually go to people who know what the hell their doing to find out real information about where bottlenecks are.
AMD's Fab 30 in Dresden is actually one of the most advanced processor fabs in the world, and they're soon moving to SOI which will give them just about everything that IBM's new plat will have.
IBM has actually never made any AMD chips to the best of my knowledge, or at least not in recent memory. I think that they may have rebranded some K6's a while back and sold those under their own name, and they definitely packaged some K6's that AMD made. They also helped AMD get their production lines at their old plant running at more acceptable levels (when the K6 first came out, AMD sucked at production). However I don't believe that IBM ever produced even a single AMD processor die for retail sales.
FWIW AMD is now planning on outsourcing some of their production to UMC anyway, so IBM would be kinda redundant.
Visual Studio.NET contains optimizations for both AMD and Intel processors.
As far as applications go though, they tend to have very few optimizations, and those optimizations that they do have are rarely processor specific except in a few special cases for show.
The reason why optimizing for a specific processor doesn't make much sense is because they change. P4 optimizations are VERY different from PIII optimizations, which in turn are different from Athlon optimizations. AMD's upcoming Hammer chips is based on the Athlon core and should have similar optimizations to it, but it's on-chip memory controller will throw a whole new monkey wrench into the mix of things (though this one is a VERY good monkey wrench:> ).
I figure that AMD will have a tough time making it too much beyond 2.5GHz.
They really struggled to get their 180nm process producing chips as fast as they did (1733MHz). With their 130nm process, they should get more speed, but I wouldn't hold my breath for a dramatic speed increase, maybe something on the order of 50%. That would take them to 2.6GHz.
Now, that being said, everyone seems to be overclocking these new AthlonXP 2600+ chips up to 2.4-2.5GHz, which is a good sign. However, overclocking does not make a finished product, so I suspect that AMD still has some work to do.
On the upside for AMD, they don't really need the AthlonXP to compete at the top-end for much longer. The "8th generation Athlon", aka the Clawhammer is set to replace the AthlonXP as AMD's high-end chip in about 5 months time. AMD is already moving the AthlonXP down into the lower end where it will compete directly against the Intel Celeron, which is currently limited to only 1.8GHz on an underperforming design (a P4 core with only 128K of L2 cache?! What were they thinking!?!) With the new processor core, the AthlonXP should quickly become a fairly cheap chip to produce (the core is only 84mm^2, which is quite a bit less then the size of the Celeron). The Socket A platform is also fairly mature and there are plenty of low-cost motherboards available.
You are wrong, at least to a certain extent. The power consumption numbers for the two chips are widely publicized at AMD's and Intel's own websites. I listed a few of these numbers in an earlier message.
Long story short, the P4 and the AthlonXP consume VERY comperable amounts of power, and given that neither of these chips is giving off any of that power as light or sound or anything else, it all ends up as heat.
It doesn't take all that much to cool an AthlonXP, just a nice big heatsink and fan, similar to the one that you would use for a P4. The "AMD needs a loud fan" myth mainly stemmed from the fact that all the early Athlon heatsinks were relatively small 60x60mm ones, and people tried to overclock the hell out of the chips by throwing ridiculous 6800+ rpm fans on them. There are now plenty of 70x70mm or 80x80mm heatsinks out there (the same size as virtually all P4 heatsinks) which will effectively cool even the most power hungry of all the Athlon chips (the Athlon 1.4GHz or AthlonXP 2100+).
AMD just exchanged one absolutely meaningless measure of performance (clock rate) for another absolutely meaningless measure of performance (model number).
The funny thing is that some people actually get upset by this, thinking that they were somehow ripped off because AMD's meaningless number isn't the same as Intel's meaningless number.
Either way, it worked for AMD. After introducing their model numbers, the average price for their processors went up by a fair margin.
Note: Intel only lists their "Thermal Design Power", which they don't really define exactly. For the Willamette CPU the TDP was defined (semi-arbitrarily) as being 75% of the theoretical maximum power, however that calculation may be different for the Northwood. Basically it's somewhere between the "typical" and "maximum" numbers that AMD lists. Some applications WILL exceed Intel's Thermal Design Power, though they're only likely to do so for a short period of time.
So, where does this all leave us? Well, first off, the original poster is correct that the AthlonXP 1800+ does produce more heat than a 2.2GHz P4, though I'm not sure that "a fair whack" is entirely accurate. The difference is actually only somewhere around 18% for the Palomino (which the OP likely has), and now that the Thoroughbreds have started to ship in volume, the AMD chip actually dissipates LESS heat.
However, simple power requirements aren't always enough. First off, the P4 has a much wider range of power use. When fully loaded down it uses about the same amount of power as an Athlon, but while at much lower load levels, it's power requirements are less. Secondly, and perhaps more importantly, P4's use almost exclusvely 70x70mm or 80x80mm heatsinks, while most Athlons use a smaller 60x60mm heatsink. I slapped a nice big 80x80mm heatsink with a VERY quiet, slow spinning fan on it and it keeps my processor (AthlonXP 1700+) quite cool at all times.
There's also the matter of the die size/heat generated per mm^2 and the heat spreader. Since the Athlon's die has a much smaller surface area than that of the P4, it's heat is much more concentrated, making it somewhat harder to cool. The P4 also has an integrated heat spreader to spread out the heat more evenly, though I don't see this as a big advantage in terms of getting rid of the heat (you stick a big honking piece of metal on top of the thing anyway, which acts as a rather effective heat spreader).
Long story short, there really isn't much difference between the P4 and the AthlonXP in terms of heat they generate. Both are moderately high powered chips, signficantly higher then chips targeted towards the embedded market (even such chips as the G4 that Apple uses), however they're also quite a bit lower then the power of the server chips like the Itanium and the Power4, both of which are well beyond 100W.
There's PLENTY wrong with Tom's Hardware, but it has nothing to do with bias. It has everything to do with the fact that Tom doesn't know NEARLY as much as people seem to think he knows. He's a medical professional by trade, and only stumbled into the computer world a few years back. His benchmarking methodology leads a bit to be desired, and the conclusions he draws from these benchmarks are typically misleading if not flat out wrong.
That being said, he still does a WAY better job then most of the trade-rags and many of the other hardware websites out there (which is kinda sad).
Planned release frequency for the first Hammer's is in the 2.0GHz range, though they're hoping to clock them up quickly from there. AMD has stated this publicly many times before, though they haven't given any exact numbers to date.
At the time of the release of the first Hammer chips (very start of '03), Intel's roadmap shows them at 3.06GHz for their fastest P4. The downside for Intel though, is that the fastest chip listed for 6-8 months later (ie mid-summer next year) on their roadmap is only 3.2GHz.
Well, ok, they aren't 100% identical, but they use virtually identical cores. The only real difference is that the Xeon runs at a lower clock speed and bus speed then the fastest P4's but has "hyperthreading" (symetric multi-threading) capabilities. It also comes in a different socket and is designed to allow dual-processor use.
However, other then those relatively minor differences, the two chips are the same, and this particular Xeon is very much designed for workstation use.
Now, the Xeon MP, well that's another beast altogether (though still based on the P4 core). There's also the PIII Xeon and the PII Xeon, which are different chips again and designed for different uses.
Long story short, the name "Xeon" doesn't tell you a whole lot about what the chip is designed for. Similarly the name "Celeron" is even worse, since there have now been 5 distinctly different versions of the Celeron processor.
Slashdot Mirror
Both the terms "front side bus" and "northbridge" are rather outdated and really don't apply to the Hammer architecture at all.
"Front Side Bus" stemmed from the PPro, which had two memory data buses, one on the "front side", which connected to the memory controller and everything else, and one on the "back side" which connected to the cache. With the Hammer, the cache is integrated so the "back side" bus never leaves the die (same as with the P4 and the AthlonXP) while the memory controller is also integrated, so part of it's "front side" never leaves the chip either, it just has a memory bus. Hypertransport is a chip-to-chip interconnect that is used for the rest of the system. You can call it a "front side bus" if you like, though the term really doesn't make any sense in this context.
"Northbridge" and "southbridge" also no longer make any sense. These terms originated because they were the "north" and the "south" end of a PCI bridge, which gave the processor a way to talk to PCI devices. Of course, the functions that these chips now perform no longer have any PCI at all in them, and the bridge is entirely in the I/O chip (what some people are still calling the "south bridge"). Intel is using their Accelerated Hub Architecture instead of PCI for interconnects, while AMD will be moving to using Hypertransport again as a chip-to-chip interconnect. AMD calls their chips "hypertransport tunnels", which is a somewhat more accurate title then a PCI bridge.
FWIW the only chipsets that I'm aware of which still use actual PCI north and south bridges are the AMD 760MP(X) and the ATI Radeon chipsets. AMD uses 66MHz/64-bit PCI to interconnect their chipsets, which gives them as much bandwidth as any competing technologies. ATI, meanwhile, is using 32-bit/33MHz, which is part of the reason why their Radeon chipset will likely really stink in the desktop market (nice for laptops, useless for desktops.. but I digress)
I gotta learn to edit my posts a bit more carefully.. The above should read "still owns a house in Canada where he lives during the summer".
/. will accept my post...
Hmm.. now I gotta wait for two minutes before
YOu think that's funny, I think I lived in the guy's house last year!
:>
I guess he now lives/teaches down in the states somewhere, but still own a house in Canada where he lives, and during the school year he rents it outto students such as myself!
Great prof he may be, but not a very great landlord!
I'm not aware of any commercial MP3 decoders for Linux, at all.
Actually, Winamp released a really early alpha version of Winamp 3.0 for Linux a little while back. I remember using it, and it was TERRIBLE, barely able to play a single song without crashing, but this was at a time when the Windows version of WinAmp 3.0 wasn't particularly stable either.
Winamp does say on their web page in their FAQ that "Support for Linux and other UNIX flavors is in the works." I haven't seen it yet and it would seem that it's been moved to the back-burner, but at least it would seem that it's still on the stove-top.
I think any consparicy theory can stay within Fraunhofer itself. This same organisation is pushing to make MP3Pro as the next standard, and that too would have a licensing fee associated with it. Maybe they're just trying to level the playing field, so to speak, by charging a fee for licensing for MP3 players, while MS and RP also have some sort of licensing for their own audio format. Then hope that their well recognized "mp3" name will carry them over to the next round and their MP3Pro will win out over MS and Real.
Of course, Ogg Vorbis is the real wildcard in the deck, and that could ruin the plans of all three companies. Ogg offers quality that matches or beats the others at absolutely no cost and with no restrictions. If enough Joe-users start to know about the situation, Ogg may quickly become the dominant standard.
This may be overly obvious, but I feel it should be pointed out.
There is a VERY good reason why we have BOTH patents and copyrights. They cover two very different things.
What you talk about with software would be covered under copyright law, and NOT under patent law.
Standard discalimer: IANAL
Yes, they most definitely are. The exact nature of the licensing agreement varies somewhat for this software, though in general it is a lot MORE restrictive then the license for MPEG1 (video or audio). Actually, that's a large part of the reason why MP3 audio (mpeg1) became so popular even though at that time mpeg2 audio was already available and a well known quantity. Mpeg1 was cheap/free while mpeg2 was expensive.
Standard disclaimer: IANAL
AMD never licensed Slot 1, what they did is they "developed" a new slot that was physically identical but flipped around backwards. They called it Slot A.
AMD could NOT use the same motherboard, regarldess of the slot use. The connector was actually of no consequence at all, it was all in the bus protocol used, which Intel would NOT license to AMD at all.
As for Cyrix, they never had a license either, they just used the P3 socket all on their own. They claimed (and still are claiming) that a cross-licensing agreement through their various owners allows them to make use of the GTL+ bus protocol that was used with the PPro, PII and PIII.
Above and beyond what the original poster wrote, take a look sometime at the "errata" or "specification update" sheets that both Intel and AMD document.
These errata sheets describe all the ways in which various processors are not compatible with the IA-32 specification. Last I checked, the P4 had 50-60 documentated incompatabilities, while the PIII had over 80. These are specifically documented situations where Intel is NOT "Intel compatible". The Athlon, meanwhile, had about 15-20.
I'll leave it as an exercise to the reader to figure out if AMD is actually MORE Intel compatible than Intel is, or if Intel just documents their incompatabilities better then AMD.
Ohh, as for point 2 above, the issue was not so much one of Intel patenting Slot 1. AMD's first Athlons used a "Slot A", which was actually just a Slot 1 connector flipped backwards. The real issue though was that Intel had patented the GTL+ bus used for PPro, PII and PIII processors. Part of the legal agreement between AMD and Intel after the 386 and 486 battle was that AMD was NOT allowed to use any Intel bus designs beyond the Pentium bus. The socket/slot used by Intel was immaterial, it was the bus protocol that AMD could not use.
Don't underestimate the potentially detrimental performance impact of the rather small L1 data cache of the P4. Something like 1 out of every 3 instructions in x86 code is a load or store, so even a relatively small difference in cache hit rates can make a BIG difference in performance. This is a large part of the reason why the P4 benefits so much from going from 256K to 512K of L2 cache, it needs it's L2 hit rate as high as possible to offset the relatively low L1 hit rate.
Just what is the exact difference in hit rates between the P4's 8K of L1 data and teh Athlons 64K L1 data cache (the other 64K is an instruction cache, more on that later)? Well that depends entirely on your application. Most numbers I've seen would tend to indicate that your 5% number isn't too far off for most applications though. However, that 5% turns into a VERY large performance difference. Even the fastest L2 cache (ie that which is used in the P4) has a 7-10 cycle latency, and main memory latency is up around 250-300 cycles these days.
The Athlon also has another slight cache advantage, in that it's cache is dual-ported, while to the best of my knowledge, the cache of the P4 is not. That means that the Athlon can be doing loads and stores at the same time, while the P4 can't. This helps the Athlon avoid some real-world latency that might not show up in the theoretical latency numbers.
Ohh, as for the total cache sizes, it's really only valid to compare 8K for teh P4 to 64K for the Athlon. The Athlon has a 64K data and 64K instruction cache. The P4 has a 8K data cache but a 12K micro-op trace cache instead of instruction cache. The trace cache, IMO, is the best/most innovative part of teh entire P4 design, as it stores already-decoded instructions in the cache rather then the x86 instructions. The end result is that this about equivalent to a 20-22K L1 instruction cache, except faster.
Anyway, long story short, I think that the P4's trace cache is great, but it's data cache is too small IMO. It allows Intel to clock the chip to very high speeds, while still keeping the memory latency low, but it makes the chip VERY dependent on the L2 cache and memory subsystem. Memory latency is HUGE these days (for comparison sake, the 386 had a memory latency of 1 clock cycle, today we have a memory latency of about 250-300 clock cycles), and with the P4's high clock speed but long pipeline, any sort of pipe stalls are a VERY bad thing for performance. Even stalling to get data from the L2 cache can be somewhat bad for the P4.
Actaully AMD had the performance lead for longer then that. They took the performance crown away from Intel the day that the Athlon was first released, since it came out at 650MHz when the fastest PIII was only 600MHz, and the Athlon was, at that time, just slightly faster clock for clock then the PIII. AMD kept the clock speed lead and increased their clock-for-clock performance over the PIII up for the next few years. Intel only just started to catch up with the P4 2.0GHz (which was released just a little bit before the AthlonXP, ie when the fastest Athlon was only at 1.4GHz).
Basically for the last 3 years (since the release of the Athlon), AMD has had the fastest x86 chips for about 2 years. Intel has had the fastest x86 chips for about 6 months, and for the remaining 6 months it's been too close to tell which was faster.
As for the P4s long pipeline, I'd say that it WAS largely responsible for increasing the performance because it allowed Intel to clock the chips so damn high. They clocked the P4 up to 2.0GHz easily on a 180nm fab process. Compare this to the PIII which they struggled to get up to 1.13GHz on the exact same 180nm process (and that took them until 1 year after their first attempt failed miserably and had to be recalled completely). AMD did slightly better with their Athlon design, but it still was only able to clock up to 1.73GHz on a 180nm process, and they had a more advanced process then Intel did in some ways (ie they were using copper interconnects).
Long story short, performance is determined (in an overly simplified way) by IPC * clock speed. With the P4, Intel looked to sacrafice IPC slightly to dramatically increase the clock speed with the goal of overall faster performance. When compared to the PIII at least, they definitely succeeded. Compare the fastest 180nm process PIII (1.13GHz) to the fastest 180nm process P4 (2.0GHz) and which do you think is faster?
FWIW, last I checked, Van actually works for VIA, in the division that designs the VIA/Cyrix processors (ie the people that VIA bought from IDT when they acquired the IDT Centaur Winchip design team).
He's no fan of Intel, though I don't know that he's exactly AMD's bitch either.
"impeccable"?! I dunno about that!
SPEC CFP2000 is by far the most widely supported benchmark, but it has it's share of flaws, just look at Sun's latest SPEC CFP2000 scores and you might notice one of them. For the Sun Blade 1900 (900MHz USIII), Sun had a rather abysmal CFP score, with the Sun Blade 1900 Cu (900MHz USIII), they were suddenly quite competative. Hugely improved compiler right?! Wrong. Actually they only improved by 0-15% on most benchmarks (about what could be expected with a slightly better compiler, ie what you could expect in the real world), however their CFP score improved by over 50%. Why is that? Well ONE single sub-bench of CFP (179.art) was increased by a remakable 560%! The end result is that the USIII looks like a rather fast chip at floating point, when it's actually butt-slow (WAY slower then either the Athlon or the P4) at everything except for one particular Fortran application. This isn't to say that Sun's score is invalid, simply that it doesn't take much to really skew the scores of ANY benchmark, including SPEC CFP.
I've also critized SPEC in the past for being a bit to focused on large datasets. For example, the 171.swim benchmark is essentially a memory bandwidth test taken from some shallow water modeling code. Now, that isn't to say that memory bandwidth isn't important for floating point and scientific applications (if it weren't IBM wouldn't have thrown a whole boatload of bandwidth at their Power4), simply that SPEC seems to have over-emphasized this aspect. I think the reason for this is that SPEC CPU95 was just the opposite, and often critized for emphasizing SMALL datasets too much, and therefore become almost completely a test of the cache architecture of the processor in many cases. For CPU2000, it seems like they over-corrected in my mind.
Long story short, if your floating point work involves small datasets, the Athlons MUCH larger L1 cache and 3 floating point execution units will crunch the code much faster. On large datasets, the P4's higher bus and memory bandwidth and larger L2 cache will crunch the code faster.
You're quite correct in that saying that the P4 has a weak FPU is definitely wrong. The chip actually is VERY good at floating point calculations, better then just about anything out there. Only the Power4 and the Itanium2 are decidely faster FP number crunchers then the P4.
Over 80% of new PCs sold next year might contain P4-based cores. At the moment it's only slightly over 50% of all new PCs sold (the Athlon sells up around 20%, the PIII still gets a fair number of sales (10%?), and Celeron chips based on the PIII core are still quite common as well (20%?).
Still, when compared to the total number of PCs out there, the ~200 million P4-based PCs that will be on the market by the end of next year isn't all that big of a number. There are still a LOT of people out there using PIII, PII and Pentium systems, as well as their Celeron derivatives of such chips, not to mention all the Athlons and K6s, as well as the Hammer chips that will be out next year as well.
Long story short, there are a LOT of x86 architectures out there, and they ALL have different optimizations requirements. Since virtually no one hand tunes their own applications for a specific chip (which would require getting down to the assembly level for the most part), it's up to the compilers to optimize for a specific chip, and generally speaking, it's a LOT more effective and a lot easier to just do general optimizations rather then core-specific optimizations. General optimizations will benefit ALL the x86 chips out there, while core-specific optimizations will only benefit a small proportion of the chips for any given time frame, after which point a new chip will come out to replace that core.
Memory throughput numbers are LARGELY determined by the bandwidth of the processor bus. AMD has 2.1GB/s of processor bus bandwidth (133/266MHz DDR, 64-bits wide), while Intel has 3.2GB/s or 4.2GB/s (100/400MHz or 133/533MHz QDR, 64-bits wide). This is the reason why Intel processors score higher on memory bandwidth tests, not VIA.
Note: don't expect a review on Tom's Hardware to pick up on something like this, you have to actually go to people who know what the hell their doing to find out real information about where bottlenecks are.
AMD's Fab 30 in Dresden is actually one of the most advanced processor fabs in the world, and they're soon moving to SOI which will give them just about everything that IBM's new plat will have.
IBM has actually never made any AMD chips to the best of my knowledge, or at least not in recent memory. I think that they may have rebranded some K6's a while back and sold those under their own name, and they definitely packaged some K6's that AMD made. They also helped AMD get their production lines at their old plant running at more acceptable levels (when the K6 first came out, AMD sucked at production). However I don't believe that IBM ever produced even a single AMD processor die for retail sales.
FWIW AMD is now planning on outsourcing some of their production to UMC anyway, so IBM would be kinda redundant.
When Tom actually writes something inteligent/useful or at the very least correct, THEN I might consider believing anythign from his page.
Seriously though, how often do you rip the heatsink off of your processor while it's running?
Visual Studio .NET contains optimizations for both AMD and Intel processors.
:> ).
As far as applications go though, they tend to have very few optimizations, and those optimizations that they do have are rarely processor specific except in a few special cases for show.
The reason why optimizing for a specific processor doesn't make much sense is because they change. P4 optimizations are VERY different from PIII optimizations, which in turn are different from Athlon optimizations. AMD's upcoming Hammer chips is based on the Athlon core and should have similar optimizations to it, but it's on-chip memory controller will throw a whole new monkey wrench into the mix of things (though this one is a VERY good monkey wrench
I figure that AMD will have a tough time making it too much beyond 2.5GHz.
They really struggled to get their 180nm process producing chips as fast as they did (1733MHz). With their 130nm process, they should get more speed, but I wouldn't hold my breath for a dramatic speed increase, maybe something on the order of 50%. That would take them to 2.6GHz.
Now, that being said, everyone seems to be overclocking these new AthlonXP 2600+ chips up to 2.4-2.5GHz, which is a good sign. However, overclocking does not make a finished product, so I suspect that AMD still has some work to do.
On the upside for AMD, they don't really need the AthlonXP to compete at the top-end for much longer. The "8th generation Athlon", aka the Clawhammer is set to replace the AthlonXP as AMD's high-end chip in about 5 months time. AMD is already moving the AthlonXP down into the lower end where it will compete directly against the Intel Celeron, which is currently limited to only 1.8GHz on an underperforming design (a P4 core with only 128K of L2 cache?! What were they thinking!?!) With the new processor core, the AthlonXP should quickly become a fairly cheap chip to produce (the core is only 84mm^2, which is quite a bit less then the size of the Celeron). The Socket A platform is also fairly mature and there are plenty of low-cost motherboards available.
You are wrong, at least to a certain extent. The power consumption numbers for the two chips are widely publicized at AMD's and Intel's own websites. I listed a few of these numbers in an earlier message.
Long story short, the P4 and the AthlonXP consume VERY comperable amounts of power, and given that neither of these chips is giving off any of that power as light or sound or anything else, it all ends up as heat.
It doesn't take all that much to cool an AthlonXP, just a nice big heatsink and fan, similar to the one that you would use for a P4. The "AMD needs a loud fan" myth mainly stemmed from the fact that all the early Athlon heatsinks were relatively small 60x60mm ones, and people tried to overclock the hell out of the chips by throwing ridiculous 6800+ rpm fans on them. There are now plenty of 70x70mm or 80x80mm heatsinks out there (the same size as virtually all P4 heatsinks) which will effectively cool even the most power hungry of all the Athlon chips (the Athlon 1.4GHz or AthlonXP 2100+).
AMD just exchanged one absolutely meaningless measure of performance (clock rate) for another absolutely meaningless measure of performance (model number).
The funny thing is that some people actually get upset by this, thinking that they were somehow ripped off because AMD's meaningless number isn't the same as Intel's meaningless number.
Either way, it worked for AMD. After introducing their model numbers, the average price for their processors went up by a fair margin.
I know people always hate actual REAL facts as opposed to anecdotal stories, but here we go anyway:
Power dissipation figures from both AMD and Intel's websites:
AthlonXP 1800+ (Palomino) : 59.2W / 66.0W (Typ / Max)
AthlonXP 1800+ (Thoroughbred A) : 46.3W / 51.0W
AthlonXP 2100+ (Palomino) : 64.3W / 72.0W
AthlonXP 2200+ (Thoroughbred A) : 61.7W / 67.9W
AthlonXP 2600+ (Thoroughbred B) : 62.0W / 68.3W *
Note: AthlonXP 2600+ numbers are from www.aceshardware.com since AMD doesn't list them in their datasheets yet.
Now for Intel's numbers:
P4 2.0GHz (Willamette) : 75.3W (TDP)
P4 2.0GHz (Northwood) : 52.4W
P4 2.2GHz (Northwood) : 55.1W
P4 2.53GHz (Northwood) : 59.3W
Note: Intel only lists their "Thermal Design Power", which they don't really define exactly. For the Willamette CPU the TDP was defined (semi-arbitrarily) as being 75% of the theoretical maximum power, however that calculation may be different for the Northwood. Basically it's somewhere between the "typical" and "maximum" numbers that AMD lists. Some applications WILL exceed Intel's Thermal Design Power, though they're only likely to do so for a short period of time.
So, where does this all leave us? Well, first off, the original poster is correct that the AthlonXP 1800+ does produce more heat than a 2.2GHz P4, though I'm not sure that "a fair whack" is entirely accurate. The difference is actually only somewhere around 18% for the Palomino (which the OP likely has), and now that the Thoroughbreds have started to ship in volume, the AMD chip actually dissipates LESS heat.
However, simple power requirements aren't always enough. First off, the P4 has a much wider range of power use. When fully loaded down it uses about the same amount of power as an Athlon, but while at much lower load levels, it's power requirements are less. Secondly, and perhaps more importantly, P4's use almost exclusvely 70x70mm or 80x80mm heatsinks, while most Athlons use a smaller 60x60mm heatsink. I slapped a nice big 80x80mm heatsink with a VERY quiet, slow spinning fan on it and it keeps my processor (AthlonXP 1700+) quite cool at all times.
There's also the matter of the die size/heat generated per mm^2 and the heat spreader. Since the Athlon's die has a much smaller surface area than that of the P4, it's heat is much more concentrated, making it somewhat harder to cool. The P4 also has an integrated heat spreader to spread out the heat more evenly, though I don't see this as a big advantage in terms of getting rid of the heat (you stick a big honking piece of metal on top of the thing anyway, which acts as a rather effective heat spreader).
Long story short, there really isn't much difference between the P4 and the AthlonXP in terms of heat they generate. Both are moderately high powered chips, signficantly higher then chips targeted towards the embedded market (even such chips as the G4 that Apple uses), however they're also quite a bit lower then the power of the server chips like the Itanium and the Power4, both of which are well beyond 100W.
There's PLENTY wrong with Tom's Hardware, but it has nothing to do with bias. It has everything to do with the fact that Tom doesn't know NEARLY as much as people seem to think he knows. He's a medical professional by trade, and only stumbled into the computer world a few years back. His benchmarking methodology leads a bit to be desired, and the conclusions he draws from these benchmarks are typically misleading if not flat out wrong.
That being said, he still does a WAY better job then most of the trade-rags and many of the other hardware websites out there (which is kinda sad).
Planned release frequency for the first Hammer's is in the 2.0GHz range, though they're hoping to clock them up quickly from there. AMD has stated this publicly many times before, though they haven't given any exact numbers to date.
At the time of the release of the first Hammer chips (very start of '03), Intel's roadmap shows them at 3.06GHz for their fastest P4. The downside for Intel though, is that the fastest chip listed for 6-8 months later (ie mid-summer next year) on their roadmap is only 3.2GHz.
The 2.2GHz Xeon IS a P4!
Well, ok, they aren't 100% identical, but they use virtually identical cores. The only real difference is that the Xeon runs at a lower clock speed and bus speed then the fastest P4's but has "hyperthreading" (symetric multi-threading) capabilities. It also comes in a different socket and is designed to allow dual-processor use.
However, other then those relatively minor differences, the two chips are the same, and this particular Xeon is very much designed for workstation use.
Now, the Xeon MP, well that's another beast altogether (though still based on the P4 core). There's also the PIII Xeon and the PII Xeon, which are different chips again and designed for different uses.
Long story short, the name "Xeon" doesn't tell you a whole lot about what the chip is designed for. Similarly the name "Celeron" is even worse, since there have now been 5 distinctly different versions of the Celeron processor.