I don't know about where you come from, but I was taught (by my father, and ex Telco engineer) PSTN has a bandwidth of 300 to 3300Hz, a total of 3KHz.
As for 56k being the limit on that, not really true. That Eris' apple of bandwidth is only achieved by taking advantage of the fact telephone networks are digital to "the last mile".
They use the 64Kbps channel as 8KHz x 7bits (they drop the lower bit for signalling and other reasons, aparently). Oh, look! 8KHz! But didn't we say 3KHz bandwidth? They're taking advantage of the fact PSTN aint what it used to be.
Yeh, I know. This isn't really on topic for VMSK/2 (which looks interesting, but time will tell), but I hate to see disinformation. (o8
The idea of the CPU having two 'personalities', and distinguishing by a bit in the code segment descriptor was suggested in the days of the PPro, by one of Intels own engineers. I don't recall their name, but I do recall they were listed as one of the original developers of the 8051.
He claimed the 'x86'ness of the PPro took 7% of the die space. For an additional 5%, they could have added a second 'personality', and begun the migration to a 'cleaner' ISA some years ago.
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I don't know about where you come from, but I was taught (by my father, and ex Telco engineer) PSTN has a bandwidth of 300 to 3300Hz, a total of 3KHz.
As for 56k being the limit on that, not really true. That Eris' apple of bandwidth is only achieved by taking advantage of the fact telephone networks are digital to "the last mile".
They use the 64Kbps channel as 8KHz x 7bits (they drop the lower bit for signalling and other reasons, aparently). Oh, look! 8KHz! But didn't we say 3KHz bandwidth? They're taking advantage of the fact PSTN aint what it used to be.
Yeh, I know. This isn't really on topic for VMSK/2 (which looks interesting, but time will tell), but I hate to see disinformation. (o8
The idea of the CPU having two 'personalities', and distinguishing by a bit in the code segment descriptor was suggested in the days of the PPro, by one of Intels own engineers. I don't recall their name, but I do recall they were listed as one of the original developers of the 8051.
He claimed the 'x86'ness of the PPro took 7% of the die space. For an additional 5%, they could have added a second 'personality', and begun the migration to a 'cleaner' ISA some years ago.
Oh well...
Three cheers for AMD! (o8