Huh?
well, I don't know what the retirement bandwidth of 21264 is, but it is no more than 4 sustained instructions per cycle... just cause you can retire 16 instructions in one cycle(and probably less) doesn't matter cause you still can only fetch 4 instructions per cycle..
G4 is probably 4 as well... P3 and P4 are both 3...
THe thing is though, I'll give you 10:1 odds that these so called 'upgrades' are oging to slow to a trickle once this system is in place...
basically, we're granting a monopoly within a monopoly... since monopolies are already unwilling to do any work to earn money, sicne they're the only game in town, now we guarantee MS money even if they don't do any improvements...
it's just not cool m8
Are you sure the FPU runs at double clock? I would assume it's just the integer units... since the FUs are already pipelined anyway you wouldn't really gain too much...
As the other person responded instructions per clock(cycle)...
back in the bad old days, you would measure things in cycles per instruction... this is pre-superscalar, meaning you only could execute a maximum of one instruciton per cycle, and since you never could really achieve this, it took more than one cycle to execute an instruction...
starting with the pentium(and I suppose the K6 but I don't really know) Intel had a superscalar design... the P5 could execute up to two instructions per cycle... I don't know what its actual IPC was, but it didn't even have a real branch predictor, so it was rather far from 2 I'm sure...
there's a huge difference between optimizing for P6 vs Athlon and the P4... P4 has significantly different pipeline design and branch prediction than current market processors...
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totally m8... I feel the same way... it's downright dodgy as hell the way they did it...
Huh? well, I don't know what the retirement bandwidth of 21264 is, but it is no more than 4 sustained instructions per cycle... just cause you can retire 16 instructions in one cycle(and probably less) doesn't matter cause you still can only fetch 4 instructions per cycle.. G4 is probably 4 as well... P3 and P4 are both 3...
Dude, you need to get some new material...
THe thing is though, I'll give you 10:1 odds that these so called 'upgrades' are oging to slow to a trickle once this system is in place... basically, we're granting a monopoly within a monopoly... since monopolies are already unwilling to do any work to earn money, sicne they're the only game in town, now we guarantee MS money even if they don't do any improvements... it's just not cool m8
I can't speak for that guy but I think the average is 3...
Are you sure the FPU runs at double clock? I would assume it's just the integer units... since the FUs are already pipelined anyway you wouldn't really gain too much...
As the other person responded instructions per clock(cycle)... back in the bad old days, you would measure things in cycles per instruction... this is pre-superscalar, meaning you only could execute a maximum of one instruciton per cycle, and since you never could really achieve this, it took more than one cycle to execute an instruction... starting with the pentium(and I suppose the K6 but I don't really know) Intel had a superscalar design... the P5 could execute up to two instructions per cycle... I don't know what its actual IPC was, but it didn't even have a real branch predictor, so it was rather far from 2 I'm sure...
there's a huge difference between optimizing for P6 vs Athlon and the P4... P4 has significantly different pipeline design and branch prediction than current market processors...