Warming stuff up isn't as cool as this baby here. it works by ionizing the air with laser, making it conductive (and shimmering blue, i might add), then passing a modulated current through the ionized air, effectively paralyzing the victim.
>You really need a thorough grounding in digital logic before you start
I learned digital design in my first semester in college, as I suspect most engineers do. It is considered the easiest course there is in electrical engineering, and it is widely accepted that novice VLSI engineers are hired with little to no relevant knowledge, at least in National Semiconductor where I worked.
>There are no higher language equivalents like Perl or VB for chip making
What about graphical verilog, where you draw the state machines themselves? What about Summit Design?
>the Camel book you get a good idea of Larry Wall's mindset
So Oreilly didn't come out with an HDL book... yet. Only goes to show engineers haven't formed a powerful community like programmers... yet (duh). This is IMHO because good engineers are simply older than good programmers. Becoming a good engineer involves 1)tinkering with expensive equipment and 2)studying some college-level physics (DO NOT TRY THIS AT HOME KIDS... yet:-)
>You really need a thorough grounding in digital logic before you start
I learned digital design in my first semester in college, as I suspect most engineers do. It is considered the easiest course there is in electrical engineering, and it is widely accepted that beginning VLSI engineers are hired with little to no knowledge, at least in National Se
>debugging a race condition in a silicon chip can take a skilled technician many many hours of painstaking labor.
Read my previous post in this thread for my comment on race-insensitive design using NCL. NCL (Null Convention Logic) is better than CBL (Clocked Boolean Logic) in this respect, as well as in reduced (~40%!!!!!) power consumption. Everyone who designs chips that would be battery operated, at least, should learn about NCL.
You can test the logic (high level) design of circuits on an FPGA, but CBL (Clocked Boolean Logic) design is sensitive to races - unlike alternative logics that are delay-insensitive (and asynchronous!) such as Theseus' Null Convention Logic (NCL).
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Warming stuff up isn't as cool as this baby here. it works by ionizing the air with laser, making it conductive (and shimmering blue, i might add), then passing a modulated current through the ionized air, effectively paralyzing the victim.
>You really need a thorough grounding in digital logic before you start
:-)
I learned digital design in my first semester in college, as I suspect most engineers do. It is considered the easiest course there is in electrical engineering, and it is widely accepted that novice VLSI engineers are hired with little to no relevant knowledge, at least in National Semiconductor where I worked.
>There are no higher language equivalents like Perl or VB for chip making
What about graphical verilog, where you draw the state machines themselves? What about Summit Design?
>the Camel book you get a good idea of Larry Wall's mindset
So Oreilly didn't come out with an HDL book... yet. Only goes to show engineers haven't formed a powerful community like programmers... yet (duh). This is IMHO because good engineers are simply older than good programmers. Becoming a good engineer involves 1)tinkering with expensive equipment and 2)studying some college-level physics (DO NOT TRY THIS AT HOME KIDS... yet
>You really need a thorough grounding in digital logic before you start
I learned digital design in my first semester in college, as I suspect most engineers do. It is considered the easiest course there is in electrical engineering, and it is widely accepted that beginning VLSI engineers are hired with little to no knowledge, at least in National Se
>debugging a race condition in a silicon chip can take a skilled technician many many hours of painstaking labor.
Read my previous post in this thread for my comment on race-insensitive design using NCL. NCL (Null Convention Logic) is better than CBL (Clocked Boolean Logic) in this respect, as well as in reduced (~40%!!!!!) power consumption. Everyone who designs chips that would be battery operated, at least, should learn about NCL.
You can test the logic (high level) design of circuits on an FPGA, but CBL (Clocked Boolean Logic) design is sensitive to races - unlike alternative logics that are delay-insensitive (and asynchronous!) such as Theseus' Null Convention Logic (NCL).
Having said that, rapid prototyping using FPGAs, such as Xilinx's contribution to artificial intelligence research can be neat.