Have a look at http://www.control-escape.com/ It's a site with information for Linux newbies and also has a Linux FAQ for Windows users at http://www.control-escape.com/lx-win-faq.html
I would label this as another pipe dream whipped up to attract interest from the public... at least until I've seen some real progress in wafer scale integration in the commercial area. The idea in it self to use whole wafers of memory, processors or combinations of them is in no way new (I even have a vague recollection of Sir Clive of ZX fame funding some project way back). After doing a little bit of digging around on the net I found an interesting article in EE Times at http://www.eet.com/news/98/1001news/switch.html)
The company mentioned in the article seems still to be alive (and can be found at http://www.hyperchip.com) and seems to be intent to develop a peta-bit router. Still no sight of a real product though.
Here are a couple of points with wafer scale integration that the article spreads some light on. The larger the circuit the less yield you will get from the process. To get around this you add circuits to detect and work around these errors - but these corrective circuits are also marred by the same amount of errors as the rest of the wafer. And adding even more redundant circuits eats up more and more of the wafer. And in the end the yields were to low to make it commercially viable.
And Richard Norman from Hyperchip says "The only commercial wafer-scale product I have heard of was a 2-Mbit, 3-inch SRAM wafer back in the days of 64-kbit SRAM chips"
Neat idea though... but until you show me the silicon I will not show you my money. But do read the article in EE Times - it's a nice piece.
One way that probably will come in handy when trying to break or at least avert bottlenecks is paralellism. And with todays prices it's also becoming more and more feasible due to the facts that low end isn't as far removed from the top end as it used to be. And the top end research is becoming more and more expensive and affected by the law of diminishing returns.
For disks: Striping will go a long way and is not that hard to implement - even today there should be a market for PCI card which could accept, for example, 4 ATA-interfaced disks. Add intelligent caching which could be more or less helpful but my experience is that the program/data I use tend to be divided in to more or less recognisable groups.
For computing: wider and/or paralelled buses combined with multiprocessor machines. Using a setup like this with a micro- or nano-kernel OS will encourage a more distributed way of programming and in a multi-processor machine with a high-speed bus you can also do dynamic load balancing a lot easier by process migration.
Slashdot Mirror
Have a look at http://www.control-escape.com/
It's a site with information for Linux newbies and
also has a Linux FAQ for Windows users at
http://www.control-escape.com/lx-win-faq.html
Hope this helps / Jari
I would label this as another pipe dream whipped up to attract interest)
from the public... at least until I've seen some real progress in wafer
scale integration in the commercial area. The idea in it self to use
whole wafers of memory, processors or combinations of them is in no way
new (I even have a vague recollection of Sir Clive of ZX fame funding some
project way back). After doing a little bit of digging around on the net
I found an interesting article in EE Times at
http://www.eet.com/news/98/1001news/switch.html
The company mentioned in the article seems still to be alive (and can be
found at http://www.hyperchip.com) and seems to be intent to develop a
peta-bit router. Still no sight of a real product though.
Here are a couple of points with wafer scale integration that the article
spreads some light on. The larger the circuit the less yield you will get
from the process. To get around this you add circuits to detect and work
around these errors - but these corrective circuits are also marred by the
same amount of errors as the rest of the wafer. And adding even more
redundant circuits eats up more and more of the wafer. And in the end the
yields were to low to make it commercially viable.
And Richard Norman from Hyperchip says "The only commercial wafer-scale
product I have heard of was a 2-Mbit, 3-inch SRAM wafer back in the days of
64-kbit SRAM chips"
Neat idea though... but until you show me the silicon I will not show you
my money. But do read the article in EE Times - it's a nice piece.
Jari
Breaking bottlenecks:
One way that probably will come in handy when trying to break or at least
avert bottlenecks is paralellism. And with todays prices it's also becoming
more and more feasible due to the facts that low end isn't as far removed from
the top end as it used to be. And the top end research is becoming more and
more expensive and affected by the law of diminishing returns.
For disks: Striping will go a long way and is not that hard to implement -
even today there should be a market for PCI card which could accept, for
example, 4 ATA-interfaced disks. Add intelligent caching which could be
more or less helpful but my experience is that the program/data I use tend
to be divided in to more or less recognisable groups.
For computing: wider and/or paralelled buses combined with multiprocessor
machines. Using a setup like this with a micro- or nano-kernel OS will
encourage a more distributed way of programming and in a multi-processor
machine with a high-speed bus you can also do dynamic load balancing a lot
easier by process migration.
Just my 20 milli-Euro. Jari