Unfortunately the smaller transistors do not
address a larger problem, the routing delay
between the transistors. Smaller feature sizes
do allow you to place more transistors if you
are able to make the connections between them
with a reasonable delay. The parasitic capacitances of the gates scales while the parasitic capacitances of the paths between them does not. This has been a serious challenge for several years now. Thats why semitech and its members have developed special processes for materials such as copper for the interconnect vs aluminum and low K dielectrics. This is done in order to reduce the interconnect delay which is proportional to the RC delay ( and now L must be added ). Copper gives you lower resistivity and the low k dielectrics reduce the capacitances which reduces the delay; the RC product. ( and
now L which reduces the instantaneous change in
current. C resists the intantaneous change
in Voltage )
Another thing that worries me is the length of
time that these new smaller gates will last w/
thinner gate oxides. I have read that IBM
increased the thickness of the gate oxide in
order to address this in servers. Intel's
products are used in systems that have been
replaced more often due to incremental improvements which might be the reason that
they have used very thin gate oxides.
I am excited about the smaller feature sizes of
transistors, though you need the caveats that I
mentioned above so that you don't try to
extrapolate when you think about what might be
possible in the future. Architecural changes
are being made by some people where you de
centralize the computing structure on the die.
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Unfortunately the smaller transistors do not address a larger problem, the routing delay between the transistors. Smaller feature sizes do allow you to place more transistors if you are able to make the connections between them with a reasonable delay. The parasitic capacitances of the gates scales while the parasitic capacitances of the paths between them does not. This has been a serious challenge for several years now. Thats why semitech and its members have developed special processes for materials such as copper for the interconnect vs aluminum and low K dielectrics. This is done in order to reduce the interconnect delay which is proportional to the RC delay ( and now L must be added ). Copper gives you lower resistivity and the low k dielectrics reduce the capacitances which reduces the delay; the RC product. ( and now L which reduces the instantaneous change in current. C resists the intantaneous change in Voltage ) Another thing that worries me is the length of time that these new smaller gates will last w/ thinner gate oxides. I have read that IBM increased the thickness of the gate oxide in order to address this in servers. Intel's products are used in systems that have been replaced more often due to incremental improvements which might be the reason that they have used very thin gate oxides. I am excited about the smaller feature sizes of transistors, though you need the caveats that I mentioned above so that you don't try to extrapolate when you think about what might be possible in the future. Architecural changes are being made by some people where you de centralize the computing structure on the die.