CoreFire(tm) is a graphical language whose primary purpose is to allow both hardware engineers and non-hardwarwe engineers to develop FPGA applications quickly.
While typical HDL's are designed to describe a fundamentally parallel process using procedural structures, CoreFire(tm) represents parallel structures as parallel structures using a data flow paradigm.
CoreFire(tm) provides a large body of ready-to-use cores that are optimized for speed on FPGA's. You don't need to understand anything about how to implement an FFT on an FPGA, all you need to do is route the data from wherever it is coming from to the core.
Where CoreFire(tm) truly shines, however, is in it's ability to create distributed control structures that are correct by construction. My experience with the development of FPGA applications is that building the computations is really the easy part. The hard part is getting the data into the system from the outside world, managing the data as it gets routed between various computations, and then getting it back out into the outside world. Typical HDL's encourage centralized control structures that have to be designed when you've got your computations all ready to go. With CoreFire(tm) you just draw out your computation as a dataflow graph and CoreFire(tm) produces the control that you need automatically.
After facing years of low productivity using conventional HDL design, we conducted a serious study of the sorts of things that would really increase our productivity and that led to the development of CoreFire(tm). In my opinion, it's the best tool for my job.
I worked in the Virginia Tech Configurable Computing Lab for many years. I hold a Ph.D. in electrical engineering from VT. Currently, I work for Annapolis Micro Systems, Inc. http://www.annapmicro.com, the world's leading FPGA-based computing solution provider. I have developed several small applications using JHDL that were used as case studies in my dissertation. I've developed large scale high-performance applications using VHDL as part of my job. I have also used a tool that, I helped pioneer, called CoreFire(tm). I can offer the following point of view about the merits of the various options.
First, VHDL was developed as a simulation language. Later, when industry discovered that what it really wanted was an automated tool that converted an HDL to a hardware design, VHDL was adopted as an input language for that process. Large portions of the VHDL language cannot, in fact, be used when the goal is to synthesize the resulting code into hardware. So, hardware development with VHDL is actually done with a subset of VHDL, typically referred to as synthesizable VHDL.
VHDL does indeed provide a higher-level approach to developing hardware. Some relatively simple language constructs can lead to a complex hardware implementation. It is, for instance, very easy to describe a state machine in VHDL and have the synthesis tool translate that state machine into gates and flip flops.
Since VHDL was not designed as a synthesis language, the translation of a VHDL construct into a hardware construct is not well defined. Each company that markets a VHDL synthesis tools approaches the problem differently. So, a given construct synthesized by one tool might lead to a well-optimized piece of hardware, while it leads to an ugly mess when synthesized by a different tool. To get reliable results, engineers that use synthesis tools must become experts in the particular synthesis tool they use.
Another disadvantage of VHDL is that it is very difficult to produce reusable code. It provides some mechanisms that seem useful for this purpose at first, but which, with experience, turn out to fall short. As a professional FPGA application developer, I've abandoned VHDL. I typically spend much too much time fighting with the language or the synthesis translation process.
So, what to use if not VHDL? The first thing that needs to be understood about JHDL is that it does not allow you to write your application in Java and then synthesize it into hardware. JHDL provides a mechanism for doing structural hardware design. So, you're not, for instance, writing a while loop in Java and having that translated into gates. What you would have to do is describe, in terms of the interconnection of the available hardware primitives and macros, the detailed hardware structure of your while loop. JHDL does not raise the accessibility of FPGA design. You still need to be a hardware engineer. You still need to understand the low-level nature of the hardware that you're building. What JHDL does is make it easier to do those things. JDHL is a Java-based library that allows you to build hardware structures using a real computing language.
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CoreFire(tm) is a graphical language whose primary purpose is to allow both hardware engineers and non-hardwarwe engineers to develop FPGA applications quickly.
While typical HDL's are designed to describe a fundamentally parallel process using procedural structures, CoreFire(tm) represents parallel structures as parallel structures using a data flow paradigm.
CoreFire(tm) provides a large body of ready-to-use cores that are optimized for speed on FPGA's. You don't need to understand anything about how to implement an FFT on an FPGA, all you need to do is route the data from wherever it is coming from to the core.
Where CoreFire(tm) truly shines, however, is in it's ability to create distributed control structures that are correct by construction. My experience with the development of FPGA applications is that building the computations is really the easy part. The hard part is getting the data into the system from the outside world, managing the data as it gets routed between various computations, and then getting it back out into the outside world. Typical HDL's encourage centralized control structures that have to be designed when you've got your computations all ready to go. With CoreFire(tm) you just draw out your computation as a dataflow graph and CoreFire(tm) produces the control that you need automatically.
After facing years of low productivity using conventional HDL design, we conducted a serious study of the sorts of things that would really increase our productivity and that led to the development of CoreFire(tm). In my opinion, it's the best tool for my job.
First, VHDL was developed as a simulation language. Later, when industry discovered that what it really wanted was an automated tool that converted an HDL to a hardware design, VHDL was adopted as an input language for that process. Large portions of the VHDL language cannot, in fact, be used when the goal is to synthesize the resulting code into hardware. So, hardware development with VHDL is actually done with a subset of VHDL, typically referred to as synthesizable VHDL.
VHDL does indeed provide a higher-level approach to developing hardware. Some relatively simple language constructs can lead to a complex hardware implementation. It is, for instance, very easy to describe a state machine in VHDL and have the synthesis tool translate that state machine into gates and flip flops.
Since VHDL was not designed as a synthesis language, the translation of a VHDL construct into a hardware construct is not well defined. Each company that markets a VHDL synthesis tools approaches the problem differently. So, a given construct synthesized by one tool might lead to a well-optimized piece of hardware, while it leads to an ugly mess when synthesized by a different tool. To get reliable results, engineers that use synthesis tools must become experts in the particular synthesis tool they use.
Another disadvantage of VHDL is that it is very difficult to produce reusable code. It provides some mechanisms that seem useful for this purpose at first, but which, with experience, turn out to fall short. As a professional FPGA application developer, I've abandoned VHDL. I typically spend much too much time fighting with the language or the synthesis translation process.
So, what to use if not VHDL? The first thing that needs to be understood about JHDL is that it does not allow you to write your application in Java and then synthesize it into hardware. JHDL provides a mechanism for doing structural hardware design. So, you're not, for instance, writing a while loop in Java and having that translated into gates. What you would have to do is describe, in terms of the interconnection of the available hardware primitives and macros, the detailed hardware structure of your while loop. JHDL does not raise the accessibility of FPGA design. You still need to be a hardware engineer. You still need to understand the low-level nature of the hardware that you're building. What JHDL does is make it easier to do those things. JDHL is a Java-based library that allows you to build hardware structures using a real computing language.