I use to read the MB's, except computer-related.
Shining a story about cpus, I imagine how many Apple employees join discussion to make cheap-ass worthless propaganda.
Same about other silicon topics, companies do build battle camps and do attack other companies.
You working at a company which has a big market share or if you're a investor, do protect your anus against Slashdot message boards.
nvidia to my knowledge implemented tile rendering technology in GeFORCE chipsets, but doesn't works with hardware T&L, this is NOT a bug?
Intel also intended to launch an OVERCLOCKED 1.13 GHz into market. Homewer, Winfast GeFORCE 2 MX cards ships overclocked and Hercules GeFORCE 2 MX400 has the memory OC'ED, but we doesn't consider this as a bug, right?
Explain to me what happens to 733 MHz (yes, those have been shipped at default clockspeeds) Coppermines and its "strange being" with certain benchmarks?
And finally, if Intel chipsets have bugs or haven't, this isn't a problem. Unlike VIA or ALi chipsets they have good default drivers from Microsoft and Intel is a good supporter (well, when Intel intends to make the hardware offers of competition appear to be buggy or crappy, when the problem is mainly software or firmware) to the Linux community.
SOI (Silicon on Insulator),.13 process, crafty enginners, scrappers from AMD doing all for Athlon to put Intel in shame.
Of course AMD will have no problem ramping up stable Athlons to higher GHz.
AMD 760 isn't a good chipset for all of you?
P4 also only does 2 FP ops/second but outperforms K7 by
about 50% on SPECfp. FP performance typically has more to do with
memory bandwidth than with the speed of the FP unit.
SPECfp? Nice benchmark, but just a benchmark . SPECfp also
reports that PII FPU is 50% faster than K6 FPU, but when you
exploits the K6 microarch the real performance is very close to
Intel's on many FP-intensive software.
I'm not talking 3dnow, Athlon or Duron, just old x87 FP code.
The reason Intel won't attach 166 or 200 MHz system bus to P!!! is this time is that it will destroy the flagship PIV if Intel does that.
P!!! can benefit from higher bus speeds cuz' it has 2 SIMD units that can process up to 8 simultaneous ops if 2 instructions were decoded, no matter its slow data moves, units' latency are smaller than Will.
P!!! is now really Celery of family, efficient but cut down. Intel could add P!!! better FSB for data prefetch when PIV achieve 3 GHz and quad-pumped 133 MHz system bus.
"Athlon + DDR is mutha-fucker, if you optimize your software for them"
Over 3 years ago, a respected flash RAM maker claimed its newest creation was been equipped w/ 2 units capable together of 1.2 GFLOPS @ 300 MHz.
- 1.2 GFLOPS???
- Quake II over 100 fps?
- MP3 encoding quick as thunder?
- 3D studio rendering over 5 complex scenes per min?
The 1st and 2nd has been shown to be true (or almost), but the 3rd... (the 1st GFLOPS running 3D studio probably came from an 1.3 GHz Athlon, if exists a 3D studio version that runs on Alpha - Alpha+WinNT? maybe... -, so CRAY machines held the crown)
Later the best-seller chipset and proeminent network adapter manufacturer launched a CPU that it claims way similar architeture, but way improved to single-unit implementaion than its dual-unit rival. Improved implementation? Now 3D studio like other CAD nightmares will run ultra-faster. Oh no... won't? Why?
- Only single-precision ops?
- Poor instruction decode performance and insufficient data bandwidth?
- No compilers for best optmization and waaaay hard to do hand picked enhancements?
The 3 objectives are true, so there are faulty engineering dept.'s. But the newer super-whooper CPUs also have problems to achieve max. performance. There are more?
- Software developers fall over the junk of x86 and x87 instruction sets.
- The own Frankenstein manufacturers doesn't know the best way possible for optimum perfomance on complex apps.
- Vicious double-precision per op use which came from the era 80-bit and 64-bit ops used rather minor precision on professional CAD (even poor physics-based CAD), home CAD, 3D modeling for macro architeture and engineering cuz' they're patterned by reference tasks that effectively needed higher precision (lab research and manufacturing industry, by example). Also, to increase precision in "single-instruction-single-data" was easier than increase FLOPS.
Ok, SIMD-FP (there is the name) this time sux (P5 FPU scked for over 4 years, K6 FPU still sux), is either manufacturers' fault like softhouses' fault.
But they at least wouldn't dare to respect the measure "GFLOPS"?
Slashdot Mirror
I use to read the MB's, except computer-related.
Shining a story about cpus, I imagine how many Apple employees join discussion to make cheap-ass worthless propaganda.
Same about other silicon topics, companies do build battle camps and do attack other companies.
You working at a company which has a big market share or if you're a investor, do protect your anus against Slashdot message boards.
nvidia to my knowledge implemented tile rendering technology in GeFORCE chipsets, but doesn't works with hardware T&L, this is NOT a bug? Intel also intended to launch an OVERCLOCKED 1.13 GHz into market. Homewer, Winfast GeFORCE 2 MX cards ships overclocked and Hercules GeFORCE 2 MX400 has the memory OC'ED, but we doesn't consider this as a bug, right? Explain to me what happens to 733 MHz (yes, those have been shipped at default clockspeeds) Coppermines and its "strange being" with certain benchmarks? And finally, if Intel chipsets have bugs or haven't, this isn't a problem. Unlike VIA or ALi chipsets they have good default drivers from Microsoft and Intel is a good supporter (well, when Intel intends to make the hardware offers of competition appear to be buggy or crappy, when the problem is mainly software or firmware) to the Linux community.
SOI (Silicon on Insulator), .13 process, crafty enginners, scrappers from AMD doing all for Athlon to put Intel in shame.
Of course AMD will have no problem ramping up stable Athlons to higher GHz.
AMD 760 isn't a good chipset for all of you?
P4 also only does 2 FP ops/second but outperforms K7 by about 50% on SPECfp. FP performance typically has more to do with memory bandwidth than with the speed of the FP unit.
SPECfp? Nice benchmark, but just a benchmark . SPECfp also reports that PII FPU is 50% faster than K6 FPU, but when you exploits the K6 microarch the real performance is very close to Intel's on many FP-intensive software.
I'm not talking 3dnow, Athlon or Duron, just old x87 FP code.
The reason Intel won't attach 166 or 200 MHz system bus to P!!! is this time is that it will destroy the flagship PIV if Intel does that. P!!! can benefit from higher bus speeds cuz' it has 2 SIMD units that can process up to 8 simultaneous ops if 2 instructions were decoded, no matter its slow data moves, units' latency are smaller than Will. P!!! is now really Celery of family, efficient but cut down. Intel could add P!!! better FSB for data prefetch when PIV achieve 3 GHz and quad-pumped 133 MHz system bus. "Athlon + DDR is mutha-fucker, if you optimize your software for them"
Over 3 years ago, a respected flash RAM maker claimed its newest creation was been equipped w/ 2 units capable together of 1.2 GFLOPS @ 300 MHz.
- 1.2 GFLOPS???
- Quake II over 100 fps?
- MP3 encoding quick as thunder?
- 3D studio rendering over 5 complex scenes per min?
The 1st and 2nd has been shown to be true (or almost), but the 3rd... (the 1st GFLOPS running 3D studio probably came from an 1.3 GHz Athlon, if exists a 3D studio version that runs on Alpha - Alpha+WinNT? maybe... -, so CRAY machines held the crown)
Later the best-seller chipset and proeminent network adapter manufacturer launched a CPU that it claims way similar architeture, but way improved to single-unit implementaion than its dual-unit rival. Improved implementation? Now 3D studio like other CAD nightmares will run ultra-faster. Oh no... won't? Why?
- Only single-precision ops?
- Poor instruction decode performance and insufficient data bandwidth?
- No compilers for best optmization and waaaay hard to do hand picked enhancements?
The 3 objectives are true, so there are faulty engineering dept.'s. But the newer super-whooper CPUs also have problems to achieve max. performance. There are more?
- Software developers fall over the junk of x86 and x87 instruction sets.
- The own Frankenstein manufacturers doesn't know the best way possible for optimum perfomance on complex apps.
- Vicious double-precision per op use which came from the era 80-bit and 64-bit ops used rather minor precision on professional CAD (even poor physics-based CAD), home CAD, 3D modeling for macro architeture and engineering cuz' they're patterned by reference tasks that effectively needed higher precision (lab research and manufacturing industry, by example). Also, to increase precision in "single-instruction-single-data" was easier than increase FLOPS.
Ok, SIMD-FP (there is the name) this time sux (P5 FPU scked for over 4 years, K6 FPU still sux), is either manufacturers' fault like softhouses' fault.
But they at least wouldn't dare to respect the measure "GFLOPS"?