From what you say I don't think that you have read everything at the sight. Some of your "facts" came from other places.
The small web appliance software was small because it was for an embedded deviced and it was to its advantage that it had about on tenth of the memory usage of next nearest compeditor's software with similar features.
We did benchmark on a number of real computing problems and did compare output to RISC, DSP and desktop chips like Pentium. Although we didn't
claim to target the full range of applications
that all architectures target. You have
identified some that we didn't target and that
are not appropriate and you have outlined
inappropriate approaches for software.
Pick some other scalable 60,000 MIP/$
chip and compare the two.
Evasive? It is easy to get lost in the
megabytes of stuff that is there. I have
fifteen years of history, information on
a number of chips, software, tutorals,
chip simulators and emulators, programming tutorials with examples, transcripts
of presentations, videos, and of course
essays. If you don't like my essays that
try to explain the big picture read
Chuck's essays or watch the videos of
his presentations.
When Chuck published all the menus in OKAD
and all the functions, some equations and
some examples of code I put it at my
site. He was not free to publish all the
details. I have used OKAD. Can I
answer any of your questions about it?
You have a lot to say. Some of it is true.
Some of it is not.
Having worked with Chuck on these chips for a decade and having been programming manager at the
iTV Corporation where I trained other people to
program these kinds of chips I would like to make
a few corrections. His claims about software are unrealistic for most other people, but accurately describe the software that matches well to his chips. I have many man years of experience with this. His mips claims are not inflated for his software or software that matches well to his chips. His claims were not meant to apply to the software that you describe.
I brought him the idea of parallel processing Forth chips a decade ago and have done a lot of
software and real systems since then.
Our multitasker and memory manager with
garabage collection and device managemnt
fit in 1K. The jpg file read, decode,
and display routine fit in 1K. The GUI
library fit in a couple of K. Real programs,
not bogomips.
The 1/2K memories on the current 25X prototype
is a variable that can be adjusted. More
can be done prototyping and production costs
are related to chip size and Chuck choose
to keep it small for prototyping and to demonstrate how much can fit a $1 production chip. It is not a hard limit.
People don't quite grasp the idea that with
a 2400 MIPS cpu you can route gigabit
datastreams on separare I/O pins and do
megahertz analog signals on other I/O pins
at the same time. The chip is a super
programmable I/O engine that could route
data at blinding speed in and out of all
those uncommitted I/O pins. I don't quite
know what you mean when you say it is
I/O bound. It is a lot like a bunch of
my F21 on the same die, same opcodes and
same ability to program high speed I/O.
But is hard to separate things like Chuck's
keyboard from his CAD software user interface
from the internals of his CAD to the internals
of his new Forth designs, to the internals
of his chip designs and what the chips
are capable of doing.
I worked for years doing simulations and
benchmarks and writing real code. You
can review the history of the project
and learn more about it at the
http:/www.ultratechnology.com website.
Harris developed the RTX from the Novix design.
Novix had 3 external memory busses, 2 for
stack spaces while Harris's RTX chips had
stacks as on chip register arrays.
The RTX 2000, 2001 and 2010 were the chips
they made. 2000 had the 1 cycle 16x16
multiply, 2001 didn't. 2010 is rad hard
and used in aerospace.
Dr. Phil Koopman's online book on stack
machines has all the details.
Slashdot Mirror
The small web appliance software was small because it was for an embedded deviced and it was to its advantage that it had about on tenth of the memory usage of next nearest compeditor's software with similar features.
We did benchmark on a number of real computing problems and did compare output to RISC, DSP and desktop chips like Pentium. Although we didn't claim to target the full range of applications that all architectures target. You have identified some that we didn't target and that are not appropriate and you have outlined inappropriate approaches for software.
Pick some other scalable 60,000 MIP /$
chip and compare the two.
Jeff Fox
UltraTechnology
When Chuck published all the menus in OKAD and all the functions, some equations and some examples of code I put it at my site. He was not free to publish all the details. I have used OKAD. Can I answer any of your questions about it?
Jeff Fox
UltraTechnology
Having worked with Chuck on these chips for a decade and having been programming manager at the iTV Corporation where I trained other people to program these kinds of chips I would like to make a few corrections. His claims about software are unrealistic for most other people, but accurately describe the software that matches well to his chips. I have many man years of experience with this. His mips claims are not inflated for his software or software that matches well to his chips. His claims were not meant to apply to the software that you describe.
I brought him the idea of parallel processing Forth chips a decade ago and have done a lot of software and real systems since then.
Our multitasker and memory manager with garabage collection and device managemnt fit in 1K. The jpg file read, decode, and display routine fit in 1K. The GUI library fit in a couple of K. Real programs, not bogomips.
The 1/2K memories on the current 25X prototype is a variable that can be adjusted. More can be done prototyping and production costs are related to chip size and Chuck choose to keep it small for prototyping and to demonstrate how much can fit a $1 production chip. It is not a hard limit.
People don't quite grasp the idea that with a 2400 MIPS cpu you can route gigabit datastreams on separare I/O pins and do megahertz analog signals on other I/O pins at the same time. The chip is a super programmable I/O engine that could route data at blinding speed in and out of all those uncommitted I/O pins. I don't quite know what you mean when you say it is I/O bound. It is a lot like a bunch of my F21 on the same die, same opcodes and same ability to program high speed I/O.
But is hard to separate things like Chuck's keyboard from his CAD software user interface from the internals of his CAD to the internals of his new Forth designs, to the internals of his chip designs and what the chips are capable of doing.
I worked for years doing simulations and benchmarks and writing real code.
You can review the history of the project and learn more about it at the
http:/www.ultratechnology.com website.
UltraTechnology
Jeff Fox
Harris developed the RTX from the Novix design. Novix had 3 external memory busses, 2 for stack spaces while Harris's RTX chips had stacks as on chip register arrays. The RTX 2000, 2001 and 2010 were the chips they made. 2000 had the 1 cycle 16x16 multiply, 2001 didn't. 2010 is rad hard and used in aerospace. Dr. Phil Koopman's online book on stack machines has all the details.