The "right" system design language is currently a heated discussion in the chip design community. A design language based on a mainstream software language (like JHDL on Java, or SystemC on C++) means that each of us already has the compiler installed to run a simulation. Proposals made on proprietary syntaxes (like SpecC, Rosetta, Superlog , Esterel, ECL ) mean that you have to set up a new environment off the beaten path.
On the other hand, in chip design a language is used to express a model. In a proprietary language, the compiler errors will related directly to that model (like 'port not connected'), while with a mainstream software language you will see C++ or Java errors that might have nothing to do with a modeling error.
So the answer to your question would be: if you are a hardware newbie, stick to an environment that supports you: VHDL, Verilog, or one of the new ones. If you like software engineering, go for C++ or Java.
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The "right" system design language is currently a heated discussion in the chip design community. A design language based on a mainstream software language (like JHDL on Java, or SystemC on C++) means that each of us already has the compiler installed to run a simulation. Proposals made on proprietary syntaxes (like SpecC, Rosetta , Superlog , Esterel, ECL ) mean that you have to set up a new environment off the beaten path.
On the other hand, in chip design a language is used to express a model. In a proprietary language, the compiler errors will related directly to that model (like 'port not connected'), while with a mainstream software language you will see C++ or Java errors that might have nothing to do with a modeling error. So the answer to your question would be: if you are a hardware newbie, stick to an environment that supports you: VHDL, Verilog, or one of the new ones. If you like software engineering, go for C++ or Java.