#2) Is it that Tom Pabst likes AMD or does he root for the underdog? Maybe he just doesn't like Intel.
#3) About the Matrox thing... You are comparing apples and oranges my friend. This bit about the 200 Mhz bus being 'duel 100' was not a smart comment. First of all a little math explaining the Matrox 'DuelBus': (x)(y)=xy For x=2 and y=128, xy=256. However, I believe that you are refering to the width of the bus, not to the speed of the bus. The ev6 protocol is real. Genuinely 200Mhz. It is a proven technology. Tom's math is just fine concerning the use of RDRAM.
As for point #4... Cache is cache. If you want more it costs, it always has. The thing is, what AMD claims they will do with the way the Cache is handled is very interesting. A programmable (speed) bus that is totally independent from the system bus will have a high neato factor. As I said yesterday, all that is left is to wait and see.
OK boys, check it out. I have been here in Bedrock, watching the developments of this chip since it was announced. My take is this. They could call it an "AMD Tortoise 2000" for all I care, I would still be interested.
can AMD mass produce it and meet demand? Again, who cares? As long as I can get one about a year after they come out (one step behind, yep, that's the way to go!;-) I will be happy.
Why will I be happy? Here is the supporting info that none of you geeks has mentioned since this name game came out.
From Thomas Pabst ( http://www.sysdoc.pair.com/ )
Tom thinks that AMD's K7 will be Intel's toughest competitor ever.
Here are a couple key excerpts from his article: (Actually, it is most of the article....but it was really good, what can I say?)
1) As already pretty well known, K7 and thus Slot A is not using Intel's P6 GTL+ bus protocol, but Digital's Alpha bus protocol 'EV6'. EV6 has got a lot of architectural advantages over GTL+ already, like the 'point-to-point topology' for multi-processing, but in case of the K7 it's even running at 200 MHz. This means that it looks as if K7 will be the first CPU that can really take advantage of the high bandwidth memory types like direct RDRAM and DDR SDRAM. Intel's GTL+ running at 100 MHz has a peak bandwidth of only 800 MB/s, at 133 MHz it will have only 1066 MB/s, so that you wonder why Intel's next chipset for Katmai will have direct RDRAM support. Direct RDRAM as well as DDR SDRAM running at 100 MHz offers a peak bandwidth of 1.6 GB/s and this bandwidth is only met by K7's 200 MHz EV6 bus. I guess that AMD will have to thank Intel for pushing direct RDRAM, because K7 seems to be the first CPU that will really need it.
2) K7 will have no less than 128 kb L1 cache, 64 kb data and 64 kb instruction cache. Pentium II is currently equipped with a quarter of that and it's rumored that Katmai may have at least 2x32 kb and thus half the L2 cache size of K7.
3)...AMD is also planning K7-versions with no less than 2 MB up to 8 MB (L2 cache)....The L2-cache speed will range from 1/3 to full CPU speed and it's planned to use 'normal' as well as double data rate (DDR) SRAMs.
4) Dirk Meyer, the chief engineer of AMD's K7, is an ex-Alpha guy. Thus it shouldn't surprise any of us that K7 was designed with very high clock speeds in mind. K7 is already now running at 500 MHz. By the time of the launch of K7 in 1H99 we should expect clock speeds way beyond that. K7 has very deep buffers to enable those high clock speeds, offering up to 72 x86 instructions in flight.
5)...K7 will smoke Intel's P6 FPU. K7 offers no less than 3 (three!) out-of-order, fully parallel FPU pipelines. The good old disadvantage of the non-Intel CPUs in terms of FPU-performance will be history with K7.
In an article that I found on the AMD site ( http://www.amd.com ) (duh)
written by By Mark Hachman, Electronic Buyers' News ( http://www.ebnews.com )
There is discussion about the AMD K7 performance. Here are a couple quotes:
1) Dirk Meyer, vice president of engineering for Sunnyvale, Calif.-based AMD, offered the first performance estimates for the final K7 silicon, though the tests were run by AMD...
2) As expected, the K7 will be produced at 600 MHz at the launch...
3) The K7's 8-byte-wide bus will run at 200 MHz, though 266-MHz and 400-MHz speeds may follow, Meyer said.
4) (here is the meat of the article -Fred)
Meyer compared 550-MHz and 600-MHz versions of its K7 microprocessor with 512 kilobytes of level 2 cache running at half of the microprocessor's frequency, with Intel's 550-MHz Pentium III Xeon also equipped with 512 KB of cache, but running at the full speed of the microprocessor. Meyer presented test results, displayed as a percentage of the Xeon's performance. Both chips were optimized for their respective instruction sets: Streaming SIMD Extensions (SSE) for Intel's chips, and the enhanced 3DNow instruction set for AMD.
The two K7s produced processed integers 5 percent and 15 percent faster than the Xeon, using the SPECint benchmark. In floating-point calculations, used extensively in multimedia applications -- an area where competitors have had difficulty keeping up with Intel -- the 550-MHz and 600-MHz K7 outperformed the Xeon by 35 percent and 40 percent, respectively, using the SPECfp measurement.
AMD also tested its parts using the 3DWinBench benchmark, the most clean-cut evaluation of multimedia performance. To set its chips directly against the competition, AMD substituted a 550-MHz Pentium III for the Xeon. According to AMD's results, however, both the 550- and 600-MHz K7 chips were at least 40 percent faster than the Pentium III.
--------------------------- Finally I will conclude with a few stats that I have gleaned from the AMD technology brief created for the Microprocessor Forum (1998) that was posted to the AMD site [( http://www.amd.com ) (in case you are really dense)]
1) 3 Parallel x86 instruction decoders
2) 9-issue Superscalar Microarchitecture Optimized for Hf
3) Dynamic scheduling with speculative, out-of-order execution
5) 3 Superscalar, Out of order int. Pipes each with a Int. exe unit and an address gen.
6) 3 Superscalar out of order MM pipes with 1 cycle throughput -FADD (4 cyc latency), MMX ALU (2 cyc latency), 3DNow! -FMUL (4 cyc latency), MMX ALU (inc. Mul & MAC), 3DNow! -FSTORE
7) L1 cache 64k Inst Cache and 64K Data cache, each 2-way set associative
8) Multi level TLB (24/256 - Entry I, 32/256 Entry D)
9) Two General Purpose 64-bit Load/store ports into D-Cache
10) High speed 64bit Backside L2 cache Controller -512 to 8MB -Programmable interface speeds
11) Deep Internal buffering to support pipelines and external interfaces -up to 72 instructions in flight -32 outstanding load misses -15-entry interger scheduler -36-entry floating point scheduler
Here are some interesting points of the ev6 bus:
1) point to point, clock forwarding 2) Decoupled address and data busses 3) 72bit data bus with/ecc 4) independent address and request busses 5) independent snoop bus 6) up to 20 outstanding transactions per processor 7) scaleable multiprocessing 8) separate L2 cache interface
Independent L2 and sys busses coupled with the out of order execution scheme mentioned above sets the stage for fast "movage of the nibbles"...did I mention 200Mhz for a starting bus speed.
Anyway, if you are reading this you are a true "geeks geek" and I salute you. I repeat, They could call it an "AMD Slug" and I would still be interested. Now, all we have to do is wait and see how the real world version of this "wonder-chip" actually performs. We may be left scratching our heads saying, "Damn! But, it looked good on paper....Didn't it?"
Don't be a podantic dude! Here in Bedrock if someone asks what speed your lan is it is generally ok to reply "ten megabit" or "hundred megabit" or "it depends upon the user load -- It's slower than a slug on a piece of sandpaper today!" The "per second" is understood by most "normal" nerds. I say "most" because,....er, well, this message is here isn't it?
Slashdot Mirror
#1) Sharky X is a bit pro intel, I think.
#2) Is it that Tom Pabst likes AMD or does he root for the underdog? Maybe he just doesn't like Intel.
#3) About the Matrox thing... You are comparing apples and oranges my friend. This bit about the 200 Mhz bus being 'duel 100' was not a smart comment. First of all a little math explaining the Matrox 'DuelBus': (x)(y)=xy For x=2 and y=128, xy=256. However, I believe that you are refering to the width of the bus, not to the speed of the bus. The ev6 protocol is real. Genuinely 200Mhz. It is a proven technology. Tom's math is just fine concerning the use of RDRAM.
As for point #4... Cache is cache. If you want more it costs, it always has. The thing is, what AMD claims they will do with the way the Cache is handled is very interesting. A programmable (speed) bus that is totally independent from the system bus will have a high neato factor. As I said yesterday, all that is left is to wait and see.
OK boys, check it out. I have been here in Bedrock, watching the developments of this chip since it was announced. My take is this. They could call it an "AMD Tortoise 2000" for all I care, I would still be interested.
;-) I will be happy.
...but it was really good, what can I say?)
...The L2-cache speed will range from 1/3 to full CPU speed and it's planned to use 'normal' as well as double data rate (DDR) SRAMs.
...K7 will smoke Intel's P6 FPU. K7 offers no less than 3 (three!) out-of-order, fully parallel FPU pipelines. The good old disadvantage of the non-Intel CPUs in terms of FPU-performance will be history with K7.
/ecc
...did I mention 200Mhz for a starting bus speed.
...Didn't it?"
can AMD mass produce it and meet demand? Again, who cares? As long as I can get one about a year after they come out (one step behind, yep, that's the way to go!
Why will I be happy? Here is the supporting info that none of you geeks has mentioned since this name game came out.
From Thomas Pabst ( http://www.sysdoc.pair.com/ )
Tom thinks that AMD's K7 will be Intel's toughest competitor ever.
Here are a couple key excerpts from his article: (Actually, it is most of the article.
1) As already pretty well known, K7 and thus Slot A is not using Intel's P6 GTL+ bus protocol, but Digital's Alpha bus protocol 'EV6'. EV6 has got a lot of architectural advantages over GTL+ already, like the 'point-to-point topology' for multi-processing, but in case of the K7 it's even running at 200 MHz. This means that it looks as if K7 will be the first CPU that can really take advantage of the high bandwidth memory types like direct RDRAM and DDR SDRAM. Intel's GTL+ running at 100 MHz has a peak bandwidth of only 800 MB/s, at 133 MHz it will have only 1066 MB/s, so that you wonder why Intel's next chipset for Katmai will have direct RDRAM support. Direct RDRAM as well as DDR SDRAM running at 100 MHz offers a peak bandwidth of 1.6 GB/s and this bandwidth is only met by K7's 200 MHz EV6 bus. I guess that AMD will have to thank Intel for pushing direct RDRAM, because K7 seems to be the first CPU that will really need it.
2) K7 will have no less than 128 kb L1 cache, 64 kb data and 64 kb instruction cache. Pentium II is currently equipped with a quarter of that and it's rumored that Katmai may have at least 2x32 kb and thus half the L2 cache size of K7.
3)...AMD is also planning K7-versions with no less than 2 MB up to 8 MB (L2 cache).
4) Dirk Meyer, the chief engineer of AMD's K7, is an ex-Alpha guy. Thus it shouldn't surprise any of us that K7 was designed with very high clock speeds in mind. K7 is already now running at 500 MHz. By the time of the launch of K7 in 1H99 we should expect clock speeds way beyond that. K7 has very deep buffers to enable those high clock speeds, offering up to 72 x86 instructions in flight.
5)
------------------------------------
WAIT!!! There's more!
In an article that I found on the AMD site ( http://www.amd.com ) (duh)
written by By Mark Hachman, Electronic Buyers' News ( http://www.ebnews.com )
There is discussion about the AMD K7 performance. Here are a couple quotes:
1) Dirk Meyer, vice president of engineering for Sunnyvale, Calif.-based AMD, offered the first performance estimates for the final K7 silicon, though the tests were run by AMD...
2) As expected, the K7 will be produced at 600 MHz at the launch...
3) The K7's 8-byte-wide bus will run at 200 MHz, though 266-MHz and 400-MHz speeds may follow, Meyer said.
4) (here is the meat of the article -Fred)
Meyer compared 550-MHz and 600-MHz versions of its K7 microprocessor with 512 kilobytes of level 2 cache running at half of the microprocessor's frequency, with Intel's 550-MHz Pentium III Xeon also equipped with 512 KB of cache, but running at the full speed of the microprocessor. Meyer presented test results, displayed as a percentage of the Xeon's performance. Both chips were optimized for their respective instruction sets: Streaming SIMD Extensions (SSE) for Intel's chips, and the enhanced 3DNow instruction set for AMD.
The two K7s produced processed integers 5 percent and 15 percent faster than the Xeon, using the SPECint benchmark. In floating-point calculations, used extensively in multimedia applications -- an area where competitors have had difficulty keeping up with Intel -- the 550-MHz and 600-MHz K7 outperformed the Xeon by 35 percent and 40 percent, respectively, using the SPECfp measurement.
AMD also tested its parts using the 3DWinBench benchmark, the most clean-cut evaluation of multimedia performance. To set its chips directly against the competition, AMD substituted a 550-MHz Pentium III for the Xeon. According to AMD's results, however, both the 550- and 600-MHz K7 chips were at least 40 percent faster than the Pentium III.
---------------------------
Finally I will conclude with a few stats that I have gleaned from the AMD technology brief created for the Microprocessor Forum (1998) that was posted to the AMD site [( http://www.amd.com ) (in case you are really dense)]
1) 3 Parallel x86 instruction decoders
2) 9-issue Superscalar Microarchitecture Optimized for Hf
3) Dynamic scheduling with speculative, out-of-order execution
4) 2040 entry Branch prediction table and 12 entry return stack
5) 3 Superscalar, Out of order int. Pipes each with a Int. exe unit and an address gen.
6) 3 Superscalar out of order MM pipes with 1 cycle throughput
-FADD (4 cyc latency), MMX ALU (2 cyc latency), 3DNow!
-FMUL (4 cyc latency), MMX ALU (inc. Mul & MAC), 3DNow!
-FSTORE
7) L1 cache 64k Inst Cache and 64K Data cache, each 2-way set associative
8) Multi level TLB (24/256 - Entry I, 32/256 Entry D)
9) Two General Purpose 64-bit Load/store ports into D-Cache
10) High speed 64bit Backside L2 cache Controller
-512 to 8MB
-Programmable interface speeds
11) Deep Internal buffering to support pipelines and external interfaces
-up to 72 instructions in flight
-32 outstanding load misses
-15-entry interger scheduler
-36-entry floating point scheduler
Here are some interesting points of the ev6 bus:
1) point to point, clock forwarding
2) Decoupled address and data busses
3) 72bit data bus with
4) independent address and request busses
5) independent snoop bus
6) up to 20 outstanding transactions per processor
7) scaleable multiprocessing
8) separate L2 cache interface
Independent L2 and sys busses coupled with the out of order execution scheme mentioned above sets the stage for fast "movage of the nibbles"
Anyway, if you are reading this you are a true "geeks geek" and I salute you. I repeat, They could call it an "AMD Slug" and I would still be interested. Now, all we have to do is wait and see how the real world version of this "wonder-chip" actually performs. We may be left scratching our heads saying, "Damn! But, it looked good on paper.
Don't be a podantic dude! Here in Bedrock if someone asks what speed your lan is it is generally ok to reply "ten megabit" or "hundred megabit" or "it depends upon the user load -- It's slower than a slug on a piece of sandpaper today!" The "per second" is understood by most "normal" nerds. I say "most" because, ....er, well, this message is here isn't it?
Fred
Live long and prosper!