I think the author is very confused. If the applications have to be recompiled anyway, there is really no need to have an instruction set similar to x86.
Here is my proposal, just take existing P4 or Athlon and expose its internal RISC-style OOO engine and instruction set. For example, we can use 32 64-bit GP registers, the first 8 registers map to 8 traditional x86 32-bit registers. The first 16 can map to x86-64 registers.
The 64-bit regs can hold integers, addresses, floats, doubles. We add ALU, AGU, load, store, shifter, multiplier, divider around this single register set. (this way we can share mul/div between int and flt.) The 64-bit instruction set can be very similar to Alpha (or Itanium if you really like it).
Under 32-bit mode, all extra registers will be used as renaming registers and run just like Athlon. Under 64-bit mode, it runs like Alpha with OOO super-scalar pipeline. Some special instructions and call gates can be used to switch mode quickly.
Comparing this to x86-64, my approach requires a compiler that is similar to alpha, where x86-86 needs a modified version x86 one. Since gcc have code generators for many architectures, I don't think it will be a big issue.
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I think the author is very confused. If the applications have to be recompiled anyway, there is really no need to have an instruction set similar to x86.
Here is my proposal, just take existing P4 or Athlon and expose its internal RISC-style OOO engine and instruction set. For example, we can use 32 64-bit GP registers, the first 8 registers map to 8 traditional x86 32-bit registers. The first 16 can map to x86-64 registers.
The 64-bit regs can hold integers, addresses, floats, doubles. We add ALU, AGU, load, store, shifter, multiplier, divider around this single register set.
(this way we can share mul/div between int and flt.) The 64-bit instruction set can be very similar to Alpha (or Itanium if you really like it).
Under 32-bit mode, all extra registers will be used as renaming registers and run just like Athlon. Under 64-bit mode, it runs like Alpha with OOO super-scalar pipeline. Some special instructions and call gates can be used to switch mode quickly.
Comparing this to x86-64, my approach requires a compiler that is similar to alpha, where x86-86 needs a modified version x86 one. Since gcc have code generators for many architectures, I don't think it will be a big issue.