The tradeoff with cache hierarchy is access time on hits vs. size.
You could increase the size of your L2 (or L1 for that matter), but you do this at the risk of sacrificing cycle time. This is part of the reason the P4 has such a tiny L1 D-cache.
With clock speeds climbing higher, the amount of time for a signal to traverse across a chip is no longer trivial, so retrieving data within N clock cycles is unrealistic with a large cache.
To add to that, the benefit over an L3 hit (even though it's much slower than L1 or L2) is that it's still much faster than main memory. DRAM is built for capacity.
Adding cache is somewhat of an easy way out in terms of adding performance with your transistor budget. You keep your power density reasonable and you also don't change the microarchitecture.
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The tradeoff with cache hierarchy is access time on hits vs. size.
You could increase the size of your L2 (or L1 for that matter), but you do this at the risk of sacrificing cycle time. This is part of the reason the P4 has such a tiny L1 D-cache.
With clock speeds climbing higher, the amount of time for a signal to traverse across a chip is no longer trivial, so retrieving data within N clock cycles is unrealistic with a large cache.
To add to that, the benefit over an L3 hit (even though it's much slower than L1 or L2) is that it's still much faster than main memory. DRAM is built for capacity.
Adding cache is somewhat of an easy way out in terms of adding performance with your transistor budget. You keep your power density reasonable and you also don't change the microarchitecture.
In conclusion, I think drugs are bad. The end.