Those URL's are worth visiting, especially the 1939 foto of his contraption perched in the middle of his parents' apartment. Complete with 1 HP motor (how many HP was the ENIAC?:-)). Additional discussion in back issues of c't magazine.
It gradually dawns that this thing was a flat-out Wang programmable calculator (when in doubt, Wang it!), minus the Nixie tube readouts and some built-in functions. I mean, it did floating-point!!
And not only did Zuse avoid "unreliable" vacuum tubes in favor of relays...even relays weren't good enough: he made his OWN relays!! I remember reading of one chap processing wafers in an electric frying pan. That was in the early '80s, but haven't read of anyone doing home semiconductors recently - FPGAs seem to have taken the wind out of personal innovation.
the biggest grin to the P6 for me was the use of "micro-ops" instead of what AMD called them: "RISC ops". Intel has a big problem using the R-word and, it would seem, the V-word...
They had to use a load-store type approach internally as the read-modify-write type stuff gets messy (impossible?) when trying to do multiple instructions at once. OTOH, CISC is nice for keeping code size small - it still has to crawl in thru those package pins. If you can add water later...
Don't see many cables. The $150 PC box, in a blister pak, hanging in K-Mart, will have a fixed power cord, digital graphics port, USB-like port, and maybe IR link.
Card slots, options, expansion just generates help line calls and false returns. The final "PC" may be a sealed box that's made in gizillions. The sad thing is, as the volume grows, the relative R&D expenditures for this format will overpower the other stuff. So anyone planning to "roll their own" may find the remaining parts' performance less and the prices sky-high and the selection lousy.
Maybe there WILL be a "deluxe" $250 model with more memory, bigger internal disk, and a fast serial expansion port (Firewire, FIO, NgIO, whatever). But not having that expansion cable hanging out there could cut liability insurance costs quite a bit!
The whole "motherboard" could be replaced by an integrated chip bonded onto a substrate with the maximum supported memory, video, whatever wouldn't fit onto the chip at the time. That would be smaller, cheaper to produce, and more electrically characterizable than a huge ATX-size multilayer m/b. The "m/b" itself could then be cheap 1-side PCB or enamelled steel or something.
Upgrade? Who "upgrades" their toaster? 2 slot not enough? Get a 4-slot. 4-slot not enough? SOL - contact local restaurant supply house, first checking wallet.
Ah, the Transputer, legendary money sink for many a company and a government or two.
Demand is relative. Volume is concentrated in uniprocessor low-end boxes: demand with a capital D. Makes sense to throw R&D money there.
Projections for these umpteen-way SMP and switched systems claim the big market is in "servers". I really don't see where servers need to be so tightly (and expensively) coupled vs 100BaseT or something. 'cause the SMP stuff starts needing fire-breathing PCI-X and beyond I/O bus(es!) to feed it and hot-swap cards and redundant power supplies. These are all expensive items!
One can set up a loose cluster server where one box can be smashed to bits and the others carry on transparently. Just plain, simple $500 specials. Maybe SMP is good for other things, but the marketing announcements always say "servers", not ray tracing or particle physics. If the "server" part is factored out, I wonder what the demand really is.
Making an affordable consumer 4-way or 8-way SMP box would be tough. The whole thrust of mass user PCs has been getting rid of those glue chips, those card slots, those cables.
There are other (tightly-coupled) ways to handle more than one instruction stream at once than wiring discrete CPUs with gruesome $$$ bus systems and arbitration logic.
L1 is impossible to share between processors. Yeah. But not impossible to share between multiple instruction streams, which the processors implement. All that interconnection stuff is so messy anyway. The history of messy interconnections is that it becomes small, cheap, mass-produced silicon.
We already have (uni-)processors capable of executing 4 instructions at once. It's just that the chip jocks seem to be making DOS CPUs. No reason those 4 instructions couldn't come from separate threads. Then L1 sharing is implicit. We should have something on-chip by '01 if we're lucky and Kindly Uncle Ben keeps the furnaces going. Not cheap, but a first step.
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Those URL's are worth visiting, especially the 1939 foto of his contraption perched in the middle of his parents' apartment. Complete with 1 HP motor (how many HP was the ENIAC? :-)). Additional discussion in back issues of c't magazine.
It gradually dawns that this thing was a flat-out Wang programmable calculator (when in doubt, Wang it!), minus the Nixie tube readouts and some built-in functions. I mean, it did floating-point!!
And not only did Zuse avoid "unreliable" vacuum tubes in favor of relays...even relays weren't good enough: he made his OWN relays!! I remember reading of one chap processing wafers in an electric frying pan. That was in the early '80s, but haven't read of anyone doing home semiconductors recently - FPGAs seem to have taken the wind out of personal innovation.
the biggest grin to the P6 for me was the use of "micro-ops" instead of what AMD called them: "RISC ops". Intel has a big problem using the R-word and, it would seem, the V-word...
They had to use a load-store type approach internally as the read-modify-write type stuff gets messy (impossible?) when trying to do multiple instructions at once. OTOH, CISC is nice for keeping code size small - it still has to crawl in thru those package pins. If you can add water later...
Don't see many cables. The $150 PC box, in a blister pak, hanging in K-Mart, will have a fixed power cord, digital graphics port, USB-like port, and maybe IR link.
Card slots, options, expansion just generates help line calls and false returns. The final "PC" may be a sealed box that's made in gizillions. The sad thing is, as the volume grows, the relative R&D expenditures for this format will overpower the other stuff. So anyone planning to "roll their own" may find the remaining parts' performance less and the prices sky-high and the selection lousy.
Maybe there WILL be a "deluxe" $250 model with more memory, bigger internal disk, and a fast serial expansion port (Firewire, FIO, NgIO, whatever). But not having that expansion cable hanging out there could cut liability insurance costs quite a bit!
The whole "motherboard" could be replaced by an integrated chip bonded onto a substrate with the maximum supported memory, video, whatever wouldn't fit onto the chip at the time. That would be smaller, cheaper to produce, and more electrically characterizable than a huge ATX-size multilayer m/b. The "m/b" itself could then be cheap 1-side PCB or enamelled steel or something.
Upgrade? Who "upgrades" their toaster? 2 slot not enough? Get a 4-slot. 4-slot not enough? SOL - contact local restaurant supply house, first checking wallet.
Ah, the Transputer, legendary money sink for many a company and a government or two.
Demand is relative. Volume is concentrated in uniprocessor low-end boxes: demand with a capital D. Makes sense to throw R&D money there.
Projections for these umpteen-way SMP and switched systems claim the big market is in "servers". I really don't see where servers need to be so tightly (and expensively) coupled vs 100BaseT or something. 'cause the SMP stuff starts needing fire-breathing PCI-X and beyond I/O bus(es!) to feed it and hot-swap cards and redundant power supplies. These are all expensive items!
One can set up a loose cluster server where one box can be smashed to bits and the others carry on transparently. Just plain, simple $500 specials. Maybe SMP is good for other things, but the marketing announcements always say "servers", not ray tracing or particle physics. If the "server" part is factored out, I wonder what the demand really is.
Making an affordable consumer 4-way or 8-way SMP box would be tough. The whole thrust of mass user PCs has been getting rid of those glue chips, those card slots, those cables.
There are other (tightly-coupled) ways to handle more than one instruction stream at once than wiring discrete CPUs with gruesome $$$ bus systems and arbitration logic.
L1 is impossible to share between processors. Yeah. But not impossible to share between multiple instruction streams, which the processors implement. All that interconnection stuff is so messy anyway. The history of messy interconnections is that it becomes small, cheap, mass-produced silicon.
We already have (uni-)processors capable of executing 4 instructions at once. It's just that the chip jocks seem to be making DOS CPUs. No reason those 4 instructions couldn't come from separate threads. Then L1 sharing is implicit. We should have something on-chip by '01 if we're lucky and Kindly Uncle Ben keeps the furnaces going. Not cheap, but a first step.
...some is just a good old-fashioned justice system, depending on where you live...