The lab-on-chip concept envisages such things as a disposable device smaller than a postage stamp, with the ability to steer blood and reagents around on a electrode grid or nanotubes. Mix, split, deliver to sensors. Results provided electronically to an external device. Blood work can be done on the spot without waiting for lab results. In large part these devices could be fabricated using technology very similar to that which produces the nm range features for current ICs.
Using FPGAs for an Echelon type system where maximizing GB/s is a primary goal? Unlikely.
I work on digital system designs clocked in the 150MHz region. No problem at all meeting the timing constraints on a typical 0.13um ASIC technology. We use FPGA's for testing and validation, however, and the latest and greatest FPGA's are maxing out with our designs at around 90MHz.
Now look at the clock speeds on the x86 you are using to browse this page. 3GHz maybe? How fast would this design run on FPGA (assuming it would fit)? Unlikely to reach even 1/10th the speed. Why not say to Intel/AMD/TI "You still use ASICs!?!"
In terms of speed, current FPGA technology cannot get anyway near the performance of a well optimized ASIC design (even with the same core process technology).
How about a new type of slashdot effect... we pick a few random bad words and slashdotters make sure to mention them several times in all phone conversations.
Slashdot Mirror
Or it may be your blood floating through a little nanomachine.
We have heard enough about 'System-on-a-Chip', nows its time for 'Lab-on-a-chip'
Agilent has an interesting blurb on the subject.
The lab-on-chip concept envisages such things as a disposable device smaller than a postage stamp, with the ability to steer blood and reagents around on a electrode grid or nanotubes. Mix, split, deliver to sensors. Results provided electronically to an external device. Blood work can be done on the spot without waiting for lab results. In large part these devices could be fabricated using technology very similar to that which produces the nm range features for current ICs.
Using FPGAs for an Echelon type system where maximizing GB/s is a primary goal? Unlikely.
I work on digital system designs clocked in the 150MHz region. No problem at all meeting the timing constraints on a typical 0.13um ASIC technology. We use FPGA's for testing and validation, however, and the latest and greatest FPGA's are maxing out with our designs at around 90MHz.
Now look at the clock speeds on the x86 you are using to browse this page. 3GHz maybe? How fast would this design run on FPGA (assuming it would fit)? Unlikely to reach even 1/10th the speed. Why not say to Intel/AMD/TI "You still use ASICs!?!"
In terms of speed, current FPGA technology cannot get anyway near the performance of a well optimized ASIC design (even with the same core process technology).
How about a new type of slashdot effect... we pick a few random bad words and slashdotters make sure to mention them several times in all phone conversations.