superscaler architectures are dynamic placement, dynamic issue: making it the hardware's responsibility to figure out both WHERE and WHEN to fire an instruction. this carries tremendous control and logic overhead.
TRIPS is a static placement, dynamic issue architecture: thus the compiler (or assembly language programmer) decides WHERE (IE: which ALU) to place an instruction, and the instructions fire dynamically - in this case, when all of it's inputs have arived.
similar in only the following: an effort to provide higher instruction level concurency while minimizing hardware control logic. exactly oposite as follows: VLIW instruction words articulate independence. TRIPS instructions articulate dependence. hardly a conventional superscaler. TRIPS operates on an explicit data graph execution paradigm.
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it's funny that a student of his could misspell his name. ;)
s/berger/burger/g
hardly.
superscaler architectures are dynamic placement, dynamic issue: making it the hardware's responsibility to figure out both WHERE and WHEN to fire an instruction. this carries tremendous control and logic overhead.
TRIPS is a static placement, dynamic issue architecture: thus the compiler (or assembly language programmer) decides WHERE (IE: which ALU) to place an instruction, and the instructions fire dynamically - in this case, when all of it's inputs have arived.
similar in only the following: an effort to provide higher instruction level concurency while minimizing hardware control logic. exactly oposite as follows: VLIW instruction words articulate independence. TRIPS instructions articulate dependence. hardly a conventional superscaler. TRIPS operates on an explicit data graph execution paradigm.
absolutely not. in fact, it's the opposite of a VLIW architecture (ex: Itanium). simply: VLIW: compiler specifies independence. TRIPS Datagraph Execution Model: compiler specifies dependence.