Most of this stuff is proprietary. Chip is our own design, our own ISA, etc. JVM: it's a port of Sun's HotSpot, v 1.4.2 & v 1.5.0 OS: doesn't really matter - you can't see the OS on the box, and we work with most host OS's.
- and what's a DRMAA machine? (caught in JFK waiting for a flight, so very soon no email...)
The box is a flat SMP - if a core misses in L2 it's the same cost to any piece of memory (or remote L2).
The cores are our own design, not MIPs, not ARM, etc. Simple, short in-order pipeline, decent caches (not huge) caches.
Power consumption is very low compared to the equivalent stack of P4 blades or other main-frame solution.
The first-gen box (368 cores) is about 2700 watts in an 11U rack mount. Next-gen box isn't much bigger, nor draws very much more power (a little more of both I belive).
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Most of this stuff is proprietary.
Chip is our own design, our own ISA, etc.
JVM: it's a port of Sun's HotSpot, v 1.4.2 & v 1.5.0
OS: doesn't really matter - you can't see the OS on the box, and we work with most host OS's.
- and what's a DRMAA machine?
(caught in JFK waiting for a flight, so very soon no email...)
Cliff
The box is a flat SMP - if a core misses in L2 it's the same cost to any piece of memory (or remote L2).
The cores are our own design, not MIPs, not ARM, etc. Simple, short in-order pipeline, decent caches (not huge) caches.
Power consumption is very low compared to the equivalent stack of P4 blades or other main-frame solution.
The first-gen box (368 cores) is about 2700 watts in an 11U rack mount.
Next-gen box isn't much bigger, nor draws very much more power (a little more of both I belive).
We've (Azul Systems) have long been aware that this is an issue and have reasonable liscencing worked out.
(my first SlashDot posting & I'm learning about posting-throttling)
I work for Azul - and yes the chip is real.