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We started using FPGA's in our HPC designs where I work several years ago - the designs are faster, more reliable, and quicker to design. StarBridges graphical development environment is a lot like another product sold by Anapolis Micro called Corefire.
Corefire is a java based graphical (iconic)development environment for Xilinx FPGA's. It is like anything else though sometimes programming in VHDL will be a better choice, it depends on the complexity of the design and the desired end result. But all in all we probably saved at least 6 man-months of design time using Corefire.

The 3000 gate figure is just the nand gate equivalent count, in reality it only has 128 moderately configurable cells. By comparison the FPGAs that people use for anything slightly serious start at about 600 cells (~40k gates, the cells in FPGAs are more complex). In the stuff I do (image processing mostly) the smallest FPGA I use is a xcv1000e with 27,648 cells (~1.5M gates), and this is fairly out of date.

OTOH you really don't want an FPGA in a handheld, as they are very inefficient in terms of power/heat. They get way too hot to touch running in my computer (admittedly without active cooling, but that would be difficult to achieve in a handheld anyway), and suck a huge amount of power (some of our machines with weaker 300W PSUs can't provide enough current to boot with an FPGA card in). Admittedly the parts I use are more heavyweight than you'd think of putting in a mobile device, but even the smaller ones need alot of power.

Annapolis (a slightly odd FPGA platform vendor) do a PCMCIA card called the Wildcard which apparently works in an iPaq (plus adaptor), for example used in this project for wireless encryption project. But they cost $999 :)

NSA has been a very heavy user of these for a long, long time now. Back when I was a fresh graduate student, a company in Annapolis, MD called Annapolis Micro Systems was hiring EE's with HDL/FPGA experience to work on their custom FPGA computing products. Needless to say, they were only looking for US citizens.

I don't see that company selling many FPGA custom computing boards to boat owners and Chesapeake Bay fishermen in Annapolis. NSA is only miles away, and I bet these boards have been developed specifically for their use.

Check out the company and their products, and you will see which products I'm taling about.

Concerning Annapolis Micro Systems, Inc., I would highly discourage any new college grads from considering a job there. Yes, the product is extremely cool, and the job offer will be phenomenal, but speaking from experience, the work environment is awful. Although the offer will include profit sharing, the "Calculated using a propietary function each year" means you get 0% profit sharing. The 401k matching is a joke too (less than half of a percent, and only payed out one year after you pay into the 401k). I accepted a position straight out of college based on the offer and the product, and left them less than two years later. The average employee stays with the company for less than two years.

I used to work for a company that manufactures a very similar device as an add on card for PCs. True enough, a single transistor on the FPGA in each of these devices is capable of firing much faster than the clock speed of available processors. However, this is the switching speed of a single transistor on the device. When transistors are chained together, you get a phenomenon called gate delay, which is the amount of time each transistor takes to react to its inputs before the output level is changed. So if a single transistor is 1000 times faster than the clock speed of a PII, and we chain 1000 of these transistors together, our usable clock speed is now the same as the PII. Another item of worry for the designers of the image to go on the FPGA is clock tree generation. The clock signal for the FPGA must be generated in such a way that all areas of the chip are synchronized. Very often, the clock tree is the biggest problem in the design as it skews as each route gets longer.

These devices are fantastic if you have a very specific application that you wish to design them for (e.g. Image processing, voice analysis, SETI@Home). With the ability to be reconfigured at a moments notice, they are also much more reusable than an ASIC. But don't be misled by the speeds given in the marketing info. Get a demo chip from Altera or Xilinx and play with it for a while. Then make your own judgements about speed.

There are a lot of groups working on similar stuff:

http://www.ccm.ece.vt.edu/acs_api - This is my group and I apologize for the lame web page. http://splish.ee.byu.edu These guys do very good work, especially when it comes to hardware description languages. http://www.east.isi.edu/projects/SLAAC/ We like these people too. http://www.annapmicro.com A lot of our graduates go here.

There are several more groups - you can find a more complete list on the People section of ISI's web site.

Being an IBM employee, I feel the need to stand up for the good Mr. Ayd :).

Aww, talk about sour grapes! They've hurt IBM's feelings, because IBM sells really smokin' computers too.

Seriously, I think David misclassified GRAPE 6 quite a bit. I don't think it's quite David's fault, because the article writers don't know the difference between 'supercomputer' and 'attached processor'. ABC News didn't really apply the term 'supercomputer' correctly either.

The term 'supercomputer' is more of a marketing term than anything else. Technical people only use it when they want to describe a general capability. AFAIK there is no concrete definitions of 'supercomputer', and if there were they would likely change daily. GRAPE 6, from the information I can see, is really an attached processor.

Attached processors can be an ARM chip on your network card to a GRAPE 6. Interanally, GRAPE 6 is a full custom, superscalar, massively pipelined, systolic array (say that 5 times fast). That basically means that data comes in one side of the board, and after n clock cycles the answer comes out the other side. There is no code other than a program running on the host computer which generates and consumes data, and every piece of the algorithm is done in hardware.

"What happens when the algorithm changes?" you might ask. Well, then you're screwed. You have to do a whole new board. Many boards use programmable chips as their processing elements, and can reprogram them when bugs or features get added, but these guys appear to be using ASICs. Great for speed, bad for flexibility.

Even though David Ayd was mistaken about the architecture, this idea has been around for quite a while also. The SPLASH 2 project was one of the first successes with this idea. There is also a commercial company selling boards using that idea but with completely up to date components (compared to SPLASH).

Still, in July of 1995, the GRAPE 4 became the world's fastest computer, breaking the 1 teraflop barrier with a peak speed of 1.08 TFLOPS.

Well, we really can't argue with that, can we, Mr. Ayd?

This architecture lends itself to extremely high throughput. It's no surprise that these perform so well. NSA uses architectures just like this to do it's crypto crunching. Brute forcing doesn't look so bad after trying one of these :).

Funny to see that article by the EFF. They have no idea how much they have underestimated the NSA.

I used to work for a company called Annapolis Micro Systems (Annapolis, MD). They specialize in selling high performance configurable computing boards (both VME and PCI versions). These boards are especially suited to numerically intense algorithms (image processing, encryption).

It's no big surprise that the single biggest customer of AMS is the NSA. They routinely bought Wildfire arrays (see website) by the dozens. Two guesses as to what they were using them for, and the first doesn't count...

It must be emphasized what kind of power these arrays confer. Anyone familiar with configurable computing knows several things:
1) It's not for the light of wallet.
2) It requires a hefty design overhead for each application.
3) It presents the fastest known solutions to almost every NP-complete and iterative solution problem ever posed.

I am a hardware designer by trade, and I can tell you that is almost beyond my ability to measure what kind of processing power these boards can enable, purchased in groups.

Be afraid, be very afraid...

(Author's note: from my limited knowledge of encryption, keys larger than 1024 bytes probably aren't crackable by brute force in this day).