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The Free-IP project, put together by a friend of mine, aimed to do just this. They have a 6502 design, and a RISC processor as well. Unfortunately, other contributions were sparse, and Real Work has gotten in the way of him creating and giving away any other designs.

>To encode a 10Khz note (sine wave, which means like a smooth ocean wave) that moves from volume 0% to volume 100% immediatly, 16/44.1 can only describe the change in 2 discreet steps. Imagine a 2 step stair when what we want is a pond ripple.

Sorry to say this, but an audio DAC does not do this.

I was corrected on this point once myself, so I'll help you too.

When a high-frequency sound is to be played, harmonics above the sampling rate are discarded (all instruments have harmonics, unless you like listening to test tones). When a DAC sees a strong high-to-low swing it shapes it (jeez... can't remember the name now... Q filter? Delta filter?) into a sine wave. By adding these sine-wave shapes together you get an exact representation of the sound below the maximum sampling frequency.

Basically, a pure sine wave is dead easy for a DAC to represent (no harmonics), whereas a true square wave (infinite harmonics) is impossible for a DAC to perfectly represent.

Fortunately, most instruments aren't square waves, and even so, most square waves can be reasonably approximated.

Anyways, for a more thorough (and correct) analysis, talk to your local Telecomm engineer. :)

Here's some info.

This is the best layman's explanation I've found.

There are lots of people here talking how open source won't work for hardware designs since it's so damn a) cost expensive and b) time expensive (does not allow experimenting) to get a chip design through a fab. So what? Reconfigurable hardware is out there and has been for quite some time.

You get a standard programmable logic device from some company like Altera (there are more, this is just the one I remember right now) and then you can program it with any chip design you want (within the complexity boundary set by the chip in question). These can do from 25MHz up to 100MHz, so you won't be able to replace your 1GHz Athlon with it, tough. Still it's usable for a lot of things. Remember, PCI runs at 33MHz or 66MHz. An MP3 decoder can be done with a lot less than 25MHz.

The software (Windows, since the control interface of the PLD is usually proprietary) compiles your Verilog or VHDL code into the required form which can be uploaded into the chip. So hardware can be designed much like software with the same round trip times. And no, you won't have to write an adder using NAND gates, you just say in VHDL "a And once you have a nice working design you can use the same source to get it through a fab.

But often you don't want a fab at all. Fabs are expensive and production has a long latency (something like 4 to 6 weeks). You can just give the PLD a finished ROM and use that as a production system. One MP3 player was only two months on market before being replaced by a successor, so it was shipped with PLDs. Only if you have really large numbers to produce, the product stays long enough on the market or the speed of a PLD isn't enough is a fab really cost efficient. I guess we'll see a lot more PLDs in shipped products in the future.

There are quite a number of CPUs for PLDs available already. Some PLD companies license CPU designs for use with their devices, e.g. I have an Altera APEX device here in front of me (not mine, a bit expensive) which comes with a NIOS softcore. Which is configurable: choose 16 or 32 bit, the number of address bits, how many registers, number of positions the shifter can shift in one cycle, ... depending on how much room you need on the device for your own design (I'm not a hw designer myself (yet), I have to program the NIOS).

Other designs are freely available under open source / free licenses (lots of stuff, not restricted to CPUs), including a SPARC CPU with peripherals by the European Space Agency under LGPL. If your PLD is large enough, you can put a whole computer on that chip (CPU, ROM, RAM, serial port etc.).

And for starters, you can get a complete development board with a PLD and software for about $150. A small CPU (no 32 bit thing with lots of registers) would fit, and it's enough for some hacking to get up to speed.

Some links for open source hardware: OpenCores, Free IP, Google Web Directory - Computers > Hardware > Open Source, LEON-1 (the ESA SPARC core).

See also:

Free-IP

A friend of mine runs http://www.free-ip.com. Free-ip is a lot less hype, and a lot more content. Several cores are online now, and there is some exciting new stuff ready but not yet released. Obligatory grumble, I've been trying to get Slashdot to run a link about it for months, but it never gets approved. ;)

A few more links: The Freedom CPU and Free-IP: ASIC and FPGA cores for the masses. There is also an EETimes article (by the Free-IP site owner) about the benefits of open-source hardware IP.

Yumpee

Xilinx makes a field programmable gate array which allows you to wire the thing on the fly. That is, they'll sell you a chip which contains anywhere from 100,000 gates to 1,000,000 gates which can be dynamically wired to provide all sorts of functionality, from microprocessor cores to UARTs to RAM cells. You don't need millions in fab equipment. Just one of these chips and an EEPROM programmer and some freeware software (links here) will do the trick.

It's not the same as editing masks using a VLSI design tool, but it does the trick.

Further, most people who design chips don't have or need millions in fab equipment. When I was at Caltech about a dozen years ago, I took a class on VLSI design where we simulated the results, and for the final, sent our design to a fab house which specializes in one-off fabrication for testing. One-off fabrication costs a few hundred to a few thousand per chip, but gives you a way to test your designs in hardware once your prototype checks on the simulator software.

Beyond that, you don't really even need to do this if you simply want to translate your FPGA design into an ASIC core for mass production. There are several fab houses who will take your FPGA data and turn it into an ASIC core for you by automatically laying out the chip-level logic from the FPGA data.

So no, you don't need "tens of millions of dollars worth of fab equipment." Far from it; just a couple of FPGA samples from Xilinx, and some software, and some descrete components for building prototype circuitry that uses your FPGA circuit from a company such as Electronix Express will do the trick.

And hell, just poke around the Free IP site; they've got two processor cores available for download, including one of which simulates the 6502 very well on several FPGA vendor's products.

Xilinx makes a field programmable gate array which allows you to wire the thing on the fly. That is, they'll sell you a chip which contains anywhere from 100,000 gates to 1,000,000 gates which can be dynamically wired to provide all sorts of functionality, from microprocessor cores to UARTs to RAM cells. You don't need millions in fab equipment. Just one of these chips and an EEPROM programmer and some freeware software (links here) will do the trick.

It's not the same as editing masks using a VLSI design tool, but it does the trick.

Further, most people who design chips don't have or need millions in fab equipment. When I was at Caltech about a dozen years ago, I took a class on VLSI design where we simulated the results, and for the final, sent our design to a fab house which specializes in one-off fabrication for testing. One-off fabrication costs a few hundred to a few thousand per chip, but gives you a way to test your designs in hardware once your prototype checks on the simulator software.

Beyond that, you don't really even need to do this if you simply want to translate your FPGA design into an ASIC core for mass production. There are several fab houses who will take your FPGA data and turn it into an ASIC core for you by automatically laying out the chip-level logic from the FPGA data.

So no, you don't need "tens of millions of dollars worth of fab equipment." Far from it; just a couple of FPGA samples from Xilinx, and some software, and some descrete components for building prototype circuitry that uses your FPGA circuit from a company such as Electronix Express will do the trick.

And hell, just poke around the Free IP site; they've got two processor cores available for download, including one of which simulates the 6502 very well on several FPGA vendor's products.

It's being done by Sun with the picoJava and SPARC cores.

eg3.com has a list of Open Source hardware links.

Tom Coonan has donated a free 8-bit microprocessor core to the Open Source IP community. One interesting aspect of this is that you can "build it yourself" using an FGPA booted from an EEPROM you can burn yourself.

And speaking of FGPAs, Xilinx has a whole page of IP for downloading and burning into their FGPAs here. What makes this super-spiffy is that you can write logic for these things and program them yourself--they download the gate configuration logic from an external ROM (or EPROM) or other source. In fact, many people are using these things by downloading the gate configuration from other sources, such as a data file.

The Open Source Hardware community apparently is thinking along the lines of using FGPAs to experiement with creating a various open source microprocessor cores in order to get the bugs out. Once the bugs are out, you can then create an ASIC core from the same data files and burn chips for production. What makes this strategy interesting is that probably for around $500 (or less) in hardware, you can build your own test bed. In fact, I could see building an FGPA "loader" which is basically a 6502 and a UART chip connected to your serial port which contains all the logic necessary to boot and download logic into an FGPA from your desktop as a sort of "in-circuit" emulator.

But my hardware days are behind me, at least for now...

See the Free-IP Project. Free-IP is endeavouring to supply free (both beer & speech) cores for ASIC's and FPGA's (used in UARTS, CPUs, Ethernet Controllers, etc.). The website has only been up since July and already there are two cores available, Free-DES and and Free-6502. Free-IP cores are either patent free, or patented and released (similar to the copyleft idea).

And along similar lines there's the Freedom-CPU Prject which is developing a GPL'd 64 bit CPU and motherboard.

See the Free-IP Project. Free-IP is endeavouring to supply free (both beer & speech) cores for ASIC's and FPGA's (used in UARTS, CPUs, Ethernet Controllers, etc.). The website has only been up since July and already there are two cores available, Free-DES and and Free-6502. Free-IP cores are either patent free, or patented and released (similar to the copyleft idea).

And along similar lines there's the Freedom-CPU Prject which is developing a GPL'd 64 bit CPU and motherboard.

See the Free-IP Project. Free-IP is endeavouring to supply free (both beer & speech) cores for ASIC's and FPGA's (used in UARTS, CPUs, Ethernet Controllers, etc.). The website has only been up since July and already there are two cores available, Free-DES and and Free-6502. Free-IP cores are either patent free, or patented and released (similar to the copyleft idea).

And along similar lines there's the Freedom-CPU Prject which is developing a GPL'd 64 bit CPU and motherboard.