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OpenNTPD just ignored the leap second

OpenNTPD has clearly been written by someone who doesn't understand NTP. For example, it advertises incorrect root delay and disperson values, which can cause clients to fail to achieve a majority vote, or to pick the wrong peer to synchronise against. (Earlier versions were even worse, they advertised themselves as being at stratum 0, which could cause synchronisation loops; this has thankfully been fixed, but it doesn't inspire much confidence in the authors' competence.)

I've also found OpenNTP to fail to regulate the local clock on dodgy hardware (it would oscillate wildly, with an amplitude of 3 seconds or so), in situations where the reference ntpd coped just fine.

Folks, do yourself and everyone a favour -- run the reference NTP, run chrony, heck, run some SNTP client, but please avoid OpenNTPD.

VHDL Cookbook is a good, though dated, intro.

Use ghdl to learn vhdl, without the need to have hardware, as it compiles VHDL to an executable. Icarus is similar, but for Verilog. gEDA has good tools, including the gtkwave waveform viewer. Combined, ghdl, Icarus and gtkwave are a pretty useful simulation suite. You can go a long way with simulation, since the normal design flow is to get the system 100% using simulation, then as a last step program the FPGA with maximal probability of it just working. As Bruce said, the actual partition, place and route tools are proprietary and specific to each FPGA vendor, and a google search will come up with a number of cheap FPGA boards.

Keep an eye on left field though. There is a convergence in progress between desktop CPU's, GPU's, parallel systems and FPGAs (which can be seen as an array of massively parallel simple processors). One day all I wrote may be obsolete and you will be able to program your FPGA in CUDA, or whatever results when mainstream programming figures out how to handle parallel systems properly.

VHDL Cookbook is a good, though dated, intro.

Use ghdl to learn vhdl, without the need to have hardware, as it compiles VHDL to an executable. Icarus is similar, but for Verilog. gEDA has good tools, including the gtkwave waveform viewer. Combined, ghdl, Icarus and gtkwave are a pretty useful simulation suite. You can go a long way with simulation, since the normal design flow is to get the system 100% using simulation, then as a last step program the FPGA with maximal probability of it just working. As Bruce said, the actual partition, place and route tools are proprietary and specific to each FPGA vendor, and a google search will come up with a number of cheap FPGA boards.

Keep an eye on left field though. There is a convergence in progress between desktop CPU's, GPU's, parallel systems and FPGAs (which can be seen as an array of massively parallel simple processors). One day all I wrote may be obsolete and you will be able to program your FPGA in CUDA, or whatever results when mainstream programming figures out how to handle parallel systems properly.

It is a bit thin on the ASIC side, but the simulation and development tools are picking up speed. Verilator and Icarus verilog are cool projects. Icarus can also do a bit of synthesis nowadays

In many ways schematic capture is an easier first step. You can hold off on Verilog or VHDL until you have made every flavor of flip-flop yourself. If you can get logic that has a few to several dozen gates to work first, then you can consider an HDL. And it doesn't really matter too much. There are pros and cons to each, and different industries prefer different languages. Actually different regions of the world prefer different languages too. Verilog is extremely popular in Silicon Valley, but on the East Coast you will find a lot more people using VHDL.

Many who prefer one over another do so because of features for doing verification. Until you know what verification is all about you probably won't be able to make an informed decision.

This fact makes it easy for most people: Icarus Verilog is open source, free and multi-platform. And useful for doing verification work, and also is capable of generating netlists to use with your favorite Xilinx or Altera parts. I'm not saying it's amazing or anything, but it does have some advantages for a hobbyist doing small projects.

Nope. There are decent Verilog synthesis and simulator projects( Icarus Verilog, Verilator), but no full dev suites that can replace the commercial tools.

The market is too small and the complexity too high to have spawned an open source competitor yet.

There are good open source tools for other things in the electronics space like PCB layout, but we're a long way from full FPGA pro tool replacement.

500 EEs, who know about as much about software as I do about circuit design.

Most digital design nowadays is done in a programming language such as Verilog and compiled into netlists. Given that Verilog code can easily be interpreted on a computer, there isn't much difference between a computer program and a circuit description for describing a computation; EEs can easily adapt.