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The domain http://www.theseus.com/ takes you to a page with the banner "global sensor networks. surveillance . tracking . control".

Unless I missed it, there was no mention of Theseus Logic's Null Convention Logic at all which is a real disappointment. Theseus has one of the few approaches that doesn't require a PhD-level of education to understand and design in.

Unless I missed it, there was no mention of Theseus Logic's Null Convention Logic at all which is a real disappointment. Theseus has one of the few approaches that doesn't require a PhD-level of education to understand and design in.

You've hit the nail right on the head. Async circuits aren't harder to design; they're harder to verify and debug. Historically the tools just haven't been up to it and, despite some recent breakthroughs, I'm not sure they are now. Check out the work at CalTech, Manchester, and Theseus Logic for the current state of the art.

The article mentions Theseus' approach to asynchronous design -- Null Convention Logic (NCL) -- but does not go into any detail. For more info, check out Theseus' white paper on the subject: ncl_paper.pdf. I read this a couple of years ago and thought it was fascinating. At the time, I tried to design some "primitives" that could be implemented in an FPGA to at least try out some of the ideas. Not a trivial excercise.

Logic synthesis tools are very important to modern day IC design and optimization.

That is why Theseus Logic, Inc. (mentioned about 2/3rds down in the NYTimes article) has a Strategic Alliance with Synopsys. Our patented NCL (Null Convention Logic) technology, unlike many other asynchronous technologies, is designed for maximum interoperability with existing tools, maximum design reuse and near-complete elimination of common CBL (clocked boolean logic) timing closure issues.

For those that mentioned Amulet, its project leader, as well as original ARM designer, Steve Furber is on Theseus' Advisory Board.

Please visit our web site for more information.

Disclaimer: I am an employee of Theseus Logic, Inc., who is NOT speaking on behalf of Theseus Logic in this post, nor his its content been approved by any Theseus Logic official.

-- Bryan "TheBS" Smith

Logic synthesis tools are very important to modern day IC design and optimization.

That is why Theseus Logic, Inc. (mentioned about 2/3rds down in the NYTimes article) has a Strategic Alliance with Synopsys. Our patented NCL (Null Convention Logic) technology, unlike many other asynchronous technologies, is designed for maximum interoperability with existing tools, maximum design reuse and near-complete elimination of common CBL (clocked boolean logic) timing closure issues.

For those that mentioned Amulet, its project leader, as well as original ARM designer, Steve Furber is on Theseus' Advisory Board.

Please visit our web site for more information.

Disclaimer: I am an employee of Theseus Logic, Inc., who is NOT speaking on behalf of Theseus Logic in this post, nor his its content been approved by any Theseus Logic official.

-- Bryan "TheBS" Smith

Logic synthesis tools are very important to modern day IC design and optimization.

That is why Theseus Logic, Inc. (mentioned about 2/3rds down in the NYTimes article) has a Strategic Alliance with Synopsys. Our patented NCL (Null Convention Logic) technology, unlike many other asynchronous technologies, is designed for maximum interoperability with existing tools, maximum design reuse and near-complete elimination of common CBL (clocked boolean logic) timing closure issues.

For those that mentioned Amulet, its project leader, as well as original ARM designer, Steve Furber is on Theseus' Advisory Board.

Please visit our web site for more information.

Disclaimer: I am an employee of Theseus Logic, Inc., who is NOT speaking on behalf of Theseus Logic in this post, nor his its content been approved by any Theseus Logic official.

-- Bryan "TheBS" Smith

Logic synthesis tools are very important to modern day IC design and optimization.

That is why Theseus Logic, Inc. (mentioned about 2/3rds down in the NYTimes article) has a Strategic Alliance with Synopsys. Our patented NCL (Null Convention Logic) technology, unlike many other asynchronous technologies, is designed for maximum interoperability with existing tools, maximum design reuse and near-complete elimination of common CBL (clocked boolean logic) timing closure issues.

For those that mentioned Amulet, its project leader, as well as original ARM designer, Steve Furber is on Theseus' Advisory Board.

Please visit our web site for more information.

Disclaimer: I am an employee of Theseus Logic, Inc., who is NOT speaking on behalf of Theseus Logic in this post, nor his its content been approved by any Theseus Logic official.

-- Bryan "TheBS" Smith

Logic synthesis tools are very important to modern day IC design and optimization.

That is why Theseus Logic, Inc. (mentioned about 2/3rds down in the NYTimes article) has a Strategic Alliance with Synopsys. Our patented NCL (Null Convention Logic) technology, unlike many other asynchronous technologies, is designed for maximum interoperability with existing tools, maximum design reuse and near-complete elimination of common CBL (clocked boolean logic) timing closure issues.

For those that mentioned Amulet, its project leader, as well as original ARM designer, Steve Furber is on Theseus' Advisory Board.

Please visit our web site for more information.

Disclaimer: I am an employee of Theseus Logic, Inc., who is NOT speaking on behalf of Theseus Logic in this post, nor his its content been approved by any Theseus Logic official.

-- Bryan "TheBS" Smith

>debugging a race condition in a silicon chip can take a skilled technician many many hours of painstaking labor.

Read my previous post in this thread for my comment on race-insensitive design using NCL. NCL (Null Convention Logic) is better than CBL (Clocked Boolean Logic) in this respect, as well as in reduced (~40%!!!!!) power consumption. Everyone who designs chips that would be battery operated, at least, should learn about NCL.

>debugging a race condition in a silicon chip can take a skilled technician many many hours of painstaking labor.

Read my previous post in this thread for my comment on race-insensitive design using NCL. NCL (Null Convention Logic) is better than CBL (Clocked Boolean Logic) in this respect, as well as in reduced (~40%!!!!!) power consumption. Everyone who designs chips that would be battery operated, at least, should learn about NCL.

You can test the logic (high level) design of circuits on an FPGA, but CBL (Clocked Boolean Logic) design is sensitive to races - unlike alternative logics that are delay-insensitive (and asynchronous!) such as Theseus' Null Convention Logic (NCL).

Having said that, rapid prototyping using FPGAs, such as Xilinx's contribution to artificial intelligence research can be neat.

It's coming. There is just no way to get "timing closure" (i.e. resolve all timing differences/issues) in modern CBL (clocked boolean logic) IC designs as fast as the clock is, at the features sizes out there and the number of gates they sport. Most asynchronous technologies solve a number of power and EMI/clock skew issues, but there is still in the ease of design and design reuse (most asynchronous technologies are more difficult than CBL).

Enter Theseus Logic's Null Convention Logic (NCL). A dual-rail logic implementation that has all the benefits of traditional async, but also sports an inheritly delay insensitive nature and complete reuseable design at new feature sizes, temperatures and voltages. And unlike other asyncs, any CBL designer can be easily retrained to understand NCL. IMHO, NCL is the only viable solution right now that will solve the upcoming brick wall that will hit the CBL world by 2006.

Now since I've talked about NCL in at least 5 other /. posts, I'll let you read more. I'm no NCL expert (just the sysadmin at Theseus that seconds as a support engineer), so hit the web site for the most detailed info.

-- Bryan "TheBS" Smith

In addition to the open-ended key size of Rijndael, after reading the AES Round 1 report, it looks like smart card applications were a key consideration (possible THE key?).

With smart cards, the issue is two fold. One, you need small code footprint, which both Rijndael and TwoFish did satisfy. And, two, the main means to hack smart cards is via power/EMI analysis.

Any circuit draws power and puts out EMI with the switching of its gates. Since there are power draws when they switch, the two are usually intertwined. I am familar with these because this because Theseus Logic's (my employer's) NCL (null convention logic) technology is ideal for smartcards because of its more uniform power (gates switch independently so they are not switching and drawing power at the same time) further resulting in a drastically reduced EMI signature compared to CBL (clocked boolean logic). In addition to being reduced, the power/EMI signature it looks nothing like CBL and those years of learning what CBL circuits look like from a power/EMI standpoint are not applicable to NCL at all.

TwoFish uses a very predictable addition subroutine that would put out a reguarly timed power/EMI signature. Rijndael seems to reduce its use of such easily identifyable operations (at least when analyzed under [6] in the report).

[ BTW, one thing I didn't understand was this statement about TwoFish: "During Round 1, there were a few concerns regarding the overall complexity of its design." Anyone know what they meant by this? ]

-- Bryan "TheBS" Smith

Windows 2000 is designed to market a Windows server-dependency. The IEEE Computer Society's latest August 2000 (Vol. 33, No. 8) Computer magazine featured an article called Windows 2000: A Threat to Internet Diversity and Open Standards? (PDF available to members here).

A such, you need to adopt a Windows server-free network. This includes holding off on Windows 2000 until either Samba supports its interfaces (will take some reverse engineering) or someone finds a way to have it use NIS/NIS+ for authentication -- e.g., NISGINA does for NT 4.0. At my company, Theseus Logic, we use NISGINA instead of Samba TNG (just use regular Samba 2.0.7) to deal with authentication of NT 4.0 systems.

-- Bryan "TheBS" Smith

AT&T's Virtual Network Computing (VNC) is an excellent GPL licesned product to look at. When the server is run on UNIX systems, it allows you to run upto 99 independent sessions (more if you reconfigure/recompile it) on a single UNIX system. These sessions have their own window manager, programs, etc... tailored for the user running it. Essentially, you have a full X-Session running just like if the user was directly in front of the GUI console of the workstation. The user can then connect to the session from any VNC client, whether that client is MacOS, Windows, UNIX, DOS, Palm, etc...

Using VNC instead of a traditional X-Server on the PC side has several advantages. One is the fact that a user can disconnect and reconnect their viewer on another system and not have to logout. This also means that if the VNC viewer system (e.g., Windows) crashes, their entire X-Session is still running (and can be reconnected to). VNC also works fairly well over low-speed connections (as good as X11R6.3 extensions for low-speed connections), provided you minimize background images. An additional advantage is the fact that it runs on a single port (5900 + session #) which makes SSH tunneling extremely simple (side benefit: "low-cost, more secure" remote access than most "all ports open" commercial VPN software).

I work for a company whose applications are 90% UNIX based (Theseus Logic), and that's not likely going to change soon (as EDA tool vendors are choosing Linux over NT because of the true multiuser capabilities). We use Linux and Solaris sytems to run these applications. Although we are starting to dual-boot some of our NT Workstations on our desks with Linux (although my personal workstation and all our servers are 100% Linux ;-), most of our work is done via VNC over to our headless Linux and Solaris systems. With 512MB to 1GB of RAM, we can easily accomodate 10 engineers on each system with fairly intensive engineering applications running. This has additional benefits like accomodating node-locked licenses that normally won't remote display (to another system), but will work in a VNC session (because the VNC session appears simply as display "localhost:vncsession#.0").

VNC is also a great way to slowly move to Linux. Users can spend 6 months becoming familiar with Linux use via a remote VNC session, while still running Windows on their desktop. You can also use VNC to UNIX systems so any user can run those few (or many, like us ;-) UNIX applications when needed. Again, VNC is so simplistically powerful (especially on UNIX systems), you'll never run out of uses for it.

Again, instead of trying to deal with finding a costly terminal server program, or a PC-X-Server, evalute if you really need one. If your UNIX platform supports VNC (and I seriously doubt there is a major or even minor UNIX platform where it has not been ported to), just give your users a full UNIX session with all it's goodies. Best of all, with the VNC server and all its windows/apps running on the UNIX platform itself, you have 100% native execution.

[ Side Note: Unfortunately, since Windows is not a true multiuser system (and only a bastardized one with products like Terminal Server), you cannot use the VNC server in a reversed role (multiple users on a Windows NT system). Although you can use VNC like pcAnywhere (unified single session, remote and local user both see the same and control the keyboard/mouse simultaneously). And like pcAnywhere, VNC sessions can be shared, allowing remote training, etc... (even on UNIX, with multiple sessions running) ]

-- Bryan "TheBS" Smith

I work at a chip design firm (Theseus Logic) and 90% of our applications run on Linux or Solaris all from a single Linux server (although we looking to add a 2nd server or a NetApp box). Outside of those programs used by 30-35 engineers, I spend 75% (or more) of my time messing with stupid Windows applications for the admin staff, a measly 7 people (even though the Engineers are 90% of the traffic and data).

From a $30K accounting package (Deltek Advantage) with its own NT server that cost more than our Linux box (and may require a 2nd one soon for stupid Citrix Winframe), to stupid little $2-5K/each Windows software packages here and their for inventory, stock options, etc..., I'm going up the wall. Especially when updating software (never goes right, unlike our UNIX EDA and other tools) and I pull my hair out. Everytime I bring up ERP I get told that since we've already spent >$50K plus another $50K on consultants, so we're not changing. Of course I brought up the point before we spent this money so I get the underlying "crying over spilt milk" or "quit rubbing it in my face" attitudes nowdays.

I can argue TOC with ERP, but for companies like mine that have already spent >$100K on disseparate Windows packages and don't want to pay anymore, a free/OSS package is the only way to get it in house. I sure wish companies would realize that maintaining disseperate little (and even big) Windows programs are just a pain in the @$$. I'm sorry but all it takes is 6 months of UNIX administration and sysadmins realize that UNIX maintainance is just 10x easier (thank God 90% of our engineering apps run on UNIX).

Thank God projects like GNU Enterprise and the Java-based Kontor Project have sprung up. I'd say if you want to help Linux get inside corporate America, look to donating your time on these projects. And you don't have to even be a developer to do so, I'm sure both projects are looking for a lot of bookeepers and accountants for most of the design.

-- Bryan "TheBS" Smith

These guys have an interesting way to deal with it.

They describe a way to build asynchronous ciruits (using the same design even for different fabs) that run as quickly as the gate/wire delays allow. It takes more surface elements to build the same logic, but once you take removal of the clock lines into consideration, things look a lot closer.

IMHO, the real beauty of async designs is that your bit shifter op can take 1 nanosecond, your add op can take 3 nanoseconds, and your subtract op can take 4 nanoseconds, rather than having them each take a 4 nanosecond cycle. It really disturbs me to see designs where a multiplication (inherently slower by a minimum factor of lg(bits)) takes the same amount of time as an addition.

Amulet's lead, Steve Furber (who also designed the original ARM), wrote a recent editorial coverstory called "Kicking out the Clock" in the May 2000 edition of Integrated System Design (ISD) magazine.

In the article, he used an example of a "dual-rail" logic (as opposed to "single-rail" found in most boolean-designs) call Null Convention Logic (NCL) from Theseus Logic. Theseus' NCL approach not only goes a long way to not only solving the power and noise problems (like most asynchronous), but also the greater problem of design reuse (a problem with both async and, especially, synchronous) -- the later is something Furber was quoted on in a past EE Times article (cannot seem to find it on-line anymore?).

Timing verification is becoming increasingly difficult in IC design, adding rediculous ammounts of extra effort and, in some cases, complete design failures (e.g., AMD, IBM and Intel have all had timing-related design failures). Clocks may soon disappear in favor of async designs, especially those like Theseus Logic's nearly-100% delay INsensitive NCL technology. NCL's delay INsensitive nature comes from the fact that it is NOT boolean logic based, but a new method that breaks the traditional foundation of what boolean logic was design for, mathematicians, not computers.

In addition to an "operand" and an "operator," as with traditional, human-based math, computers require a third "control" line. In synch/boolean, this is the clock. With the limitations of the speed of light, it is IMPOSSIBLE for 10M+ transistor ICs on one section of the chip to be timed synchronous with another. As such, most modern ICs have localized clocks, which further adds to design complexity.

NCL removes the clock as the control (as with most async) *BUT* it places the control back in the data flow lines themselves! NCL is a 3-state logic of "true" and "false", plus the control which is derived from NCL math to be "null" (no data). This representation is 2NCL in NCL math (see Theseus' site for more details on NCL including 4NCL and 3NCL, the later being used with most off-the-shelf tools and optimizers). In 2NCL, the lines (again, "dual-rail") puts the false value (0) on one line and true (1) on the other line *IF* voltage is present, otherwise, no voltage (or low) results in the state of "null" (again, no data). Acknoledgements are used to maintain a delay INsensitive combinational logic circuit, including the fact that NCL can be place alonside synch/boolean and maintain 100% data flow and integrity (again, totally delay INsensitive). So instead of data having to "wait" on a clock to move forward, data moves forward when it arrives! This further increases performance!

Although Theseus' NCL technology is NOT boolean based, it works with off-the-shelf synch/boolean IC design tools (unlike attempts like Cogency's), it is still CMOS-based, and it not too difficult for an engineer to learn coming from the synch/boolean world.

[Bias: I am an employee of Theseus Logic and know Mr. Furber, the Amulet lead. I am NOT an engineering lead, just a regular engineer (who seconds as the sysadmin ;-).]

-- Bryan "TheBS" Smith

Amulet's lead, Steve Furber (who also designed the original ARM), wrote a recent editorial coverstory called "Kicking out the Clock" in the May 2000 edition of Integrated System Design (ISD) magazine.

In the article, he used an example of a "dual-rail" logic (as opposed to "single-rail" found in most boolean-designs) call Null Convention Logic (NCL) from Theseus Logic. Theseus' NCL approach not only goes a long way to not only solving the power and noise problems (like most asynchronous), but also the greater problem of design reuse (a problem with both async and, especially, synchronous) -- the later is something Furber was quoted on in a past EE Times article (cannot seem to find it on-line anymore?).

Timing verification is becoming increasingly difficult in IC design, adding rediculous ammounts of extra effort and, in some cases, complete design failures (e.g., AMD, IBM and Intel have all had timing-related design failures). Clocks may soon disappear in favor of async designs, especially those like Theseus Logic's nearly-100% delay INsensitive NCL technology. NCL's delay INsensitive nature comes from the fact that it is NOT boolean logic based, but a new method that breaks the traditional foundation of what boolean logic was design for, mathematicians, not computers.

In addition to an "operand" and an "operator," as with traditional, human-based math, computers require a third "control" line. In synch/boolean, this is the clock. With the limitations of the speed of light, it is IMPOSSIBLE for 10M+ transistor ICs on one section of the chip to be timed synchronous with another. As such, most modern ICs have localized clocks, which further adds to design complexity.

NCL removes the clock as the control (as with most async) *BUT* it places the control back in the data flow lines themselves! NCL is a 3-state logic of "true" and "false", plus the control which is derived from NCL math to be "null" (no data). This representation is 2NCL in NCL math (see Theseus' site for more details on NCL including 4NCL and 3NCL, the later being used with most off-the-shelf tools and optimizers). In 2NCL, the lines (again, "dual-rail") puts the false value (0) on one line and true (1) on the other line *IF* voltage is present, otherwise, no voltage (or low) results in the state of "null" (again, no data). Acknoledgements are used to maintain a delay INsensitive combinational logic circuit, including the fact that NCL can be place alonside synch/boolean and maintain 100% data flow and integrity (again, totally delay INsensitive). So instead of data having to "wait" on a clock to move forward, data moves forward when it arrives! This further increases performance!

Although Theseus' NCL technology is NOT boolean based, it works with off-the-shelf synch/boolean IC design tools (unlike attempts like Cogency's), it is still CMOS-based, and it not too difficult for an engineer to learn coming from the synch/boolean world.

[Bias: I am an employee of Theseus Logic and know Mr. Furber, the Amulet lead. I am NOT an engineering lead, just a regular engineer (who seconds as the sysadmin ;-).]

-- Bryan "TheBS" Smith

In a self-timed circuit, the instant the gate changes, the next phase of the circuit is ready to go so there is no time "wasted" (19ns in the above example) waiting for the next clock.

This concept of uncertainty (between how much time the gate really takes to propagate and what the published maximum is) is also the reason why a small number of asynchronous lines can be faster than more synchronous lines. The more lines you have, the higher the possibility that there will be "skew" (i.e., different propagation delays) through them, hence you have to wait longer for all of them to come to the same state. The fewer the lines, the lower the skew, the less you have to wait (there is a reason why USB is a serial bus, not a parallel one).

There's some interesting reading on this topic at www.theseus.com. (I have no connection to them)

Theseus Logic have some interesting papers on asynchronous logic design on their website, not directly connected to the story, but they're interesting nonetheless.

The current way people build finite state machines is using CBL (clocked boolean logic). There is a better way to do this though, called NCL, which i came across while surfing. I studied the pdfs to the degree of being able to sythesize state machines Without Clocks: NEAT!

Two things about introducing NCL to people who do state machines for a living (electrical engineers):
1. No experienced engineer would believe you. I have tried this so many times at the last place i worked (National Semiconductors) I got tired. It is not that they don't know/trust you. Timing is just a *big* problem right now.
2. If they listen long enough to understand what you mean, they get excited (good as a starter if you have really bad news to tell them).

All "Contemporary" Logic Design is OUT OF DATE!!!

Traditional, clocked Boolean logic is flawed as numerous design failures have begun to occur - e.g. the original designs of the AMD K5/6, IBM PPC620, Intel Coppermine, etc... which set back product releases anywhere from 6-36 months

Why? Synchronizing millions of gates at near-GHz speeds is next to impossible. As such, even the Semiconductor Industry Association (SIA) knows that the industry must return to asynchronous and "clockless" logic as laid out in its 2001, 2003 and 2005 milestone plans.

We at Theseus Logic have the answer. This post if VERY COINCIDENTAL since we just annouced a STRATEGIC ALLIANCE with Motorola (Press Release Here) to bring our patented Null Convention Logic (NCL) technology to Motorola's 8 and 32-bit product designs.

Like other async technologies, NCL benefits fro async's inherit no/low-power, low-EMI emissions and high EMF tolerance. But UNLIKE TRADITIONAL ASYNC DESIGNS, NCL not only can co-exist with clock boolean logic in the same circuit, but you can use off-the-self sync design tools to design in NCL (via the use of a post-processor for many industry tools like Synopsys).

And lastly, as clocked boolean designs have to be redesigned for each feature size reduction (e.g. 0.25um -> 0.18um, etc...) and voltage variations (e.g. 3.3V vs. 2.5V, etc...), NCL circuits require LITTLE OR NO REDESIGN when new technology becomes available! As such, we call NCL designs "Timeless Solutions(TM)" because they deliver on both the delay-insensitive nature of async *AND* NCL designs can be re-used over and over again for a log period of time!

Again, visit Our Web Site to learn more about NCL technology and design. Note, content is slightly out of date, but the technology is nothing new. The technology was invented in the '70s, researched in the '80s and has finally become viable in the '90s.

The University of Central Florida has graduate programs in NCL design and technology which usually involve Theseus sponsorship and/or employment at Theseus (both during and post-educational).

-- Bryan "TheBS" Smith

All "Contemporary" Logic Design is OUT OF DATE!!!

Traditional, clocked Boolean logic is flawed as numerous design failures have begun to occur - e.g. the original designs of the AMD K5/6, IBM PPC620, Intel Coppermine, etc... which set back product releases anywhere from 6-36 months

Why? Synchronizing millions of gates at near-GHz speeds is next to impossible. As such, even the Semiconductor Industry Association (SIA) knows that the industry must return to asynchronous and "clockless" logic as laid out in its 2001, 2003 and 2005 milestone plans.

We at Theseus Logic have the answer. This post if VERY COINCIDENTAL since we just annouced a STRATEGIC ALLIANCE with Motorola (Press Release Here) to bring our patented Null Convention Logic (NCL) technology to Motorola's 8 and 32-bit product designs.

Like other async technologies, NCL benefits fro async's inherit no/low-power, low-EMI emissions and high EMF tolerance. But UNLIKE TRADITIONAL ASYNC DESIGNS, NCL not only can co-exist with clock boolean logic in the same circuit, but you can use off-the-self sync design tools to design in NCL (via the use of a post-processor for many industry tools like Synopsys).

And lastly, as clocked boolean designs have to be redesigned for each feature size reduction (e.g. 0.25um -> 0.18um, etc...) and voltage variations (e.g. 3.3V vs. 2.5V, etc...), NCL circuits require LITTLE OR NO REDESIGN when new technology becomes available! As such, we call NCL designs "Timeless Solutions(TM)" because they deliver on both the delay-insensitive nature of async *AND* NCL designs can be re-used over and over again for a log period of time!

Again, visit Our Web Site to learn more about NCL technology and design. Note, content is slightly out of date, but the technology is nothing new. The technology was invented in the '70s, researched in the '80s and has finally become viable in the '90s.

The University of Central Florida has graduate programs in NCL design and technology which usually involve Theseus sponsorship and/or employment at Theseus (both during and post-educational).

-- Bryan "TheBS" Smith

My wild guess at what Transmeta is up to some form of asynchronous logic design. A lot of the fabless chip companies have been making similar promises with that area of research. Theseus Logic and Cogency are two that come to mind. Clocked logic has its limits and the Intels and Motorolas of the world are going to hit those limits sooner or later. And barring any sudden developments in, say, quantum comptuing, asynchronous logic is the next, ahem, logical step. It's much quicker, much more flexible (didn't surprise me about the emulation speeds transmeta boasted of)and should consume less power, if done right. Transmeta, or their followers, is touting all three benefits. Asynchronous logic design actually has been around for awhile, though its always required a complexity of design that makes it more expensive to pull off. But as clocked logic is getting so complex, it might soon be the time where they'll be equivalent, cost-wise. Then again, Transmeta could be up to something *completely* different. joab