Tera Completes Acquistion of Cray

dewey writes "Tera, a new kid on the supercomputing block, has successfully completed its acquisition of the supercomputing pioneer, Cray (formerly owned by SGI). The new company will take Cray's name. Tera has a press release from a month ago that spells out some of the details of the deal. "

Comments

Tera's multithreaded architecture

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Apparently, a lot of people here like to shout "beowulf cluster" and don't understand much about the problems of massively parallel computing.

The bottleneck is inter-processor communication. If all you are doing is trying to brute force a cipher the processors are almost independent and easily reach the theoretical aggregate performance figures. But if you are doing complex physical simulations you can end up waiting for data most of the time and using only a fraction of your theoretical parallel power.

This is especially true of things that don't break down nicely into regular blocks. For a wind tunnel simulation you can assign different sections of the tunnel to different processors and each one communicates only with its neighbors with nice, predictable access patters. For something like a simulation of a car crash this will not work too well, though.

Tera's architecture is based around a high throughput communication fabric. The cost of this architecture is the latency - it can take many cycles from the time you request a piece of data stored in another processor until it traverses the switch fabric and the result comes back. To get around this problem each processor runs many threads with very fine granularity - it switches to a different thread every instruction cycle. By the time the next instruction for the same thread is scheduled for execution the results of a remote memory access are already available, without wait states. Each of these "virtual processor" threads is not particularly fast but the total throughput is very high.

This presents the programmer with a simple shared-memory multithreaded programming model. No need to reengineer your program to a specific message passing architecture supported by the target machine.

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