Dual Pentium III Xeon Review

Sander Sassen writes: "Intel has recently released its new line of Pentium III Xeon CPUs, based on their new .18 micron process. HardwareCentral takes a look at its performance, utilizing a dual CPU configuration on an Intel i840 platform with 256 MB of Rambus memory as a testbed. This Dual Pentium III Xeon review has all the details of their findings."

Comments

Re:sortof [OT] Athlon question.

[bluGill]

Rumor has it that dual athlon boards will be coming out within the enxt few months.

There is a hitch though: Linux will no support them! Thats right, Linux will not support SMP Athlons today. FreeBSD will not either. The good news is at least NT will not have support.

I think you see the problem: nobody will support them, so they won't sell, so nobody will add support, so . . .

I hope that someone overcomes that problems (and I think the board manufactures are working on NT support before they release something) When it works the Athlons will do much better SMP then any Intel offering. Seems that AMD, Cyrix (Do they make processors anymore) and the like got mad at Intel's SMP scheme and created a better one. The K-5 and cryix chips supported it, but nobody made a board to support it. I don't know if Athlon uses the same older spec or a new (alpha compatable?) spec, but I do know the Athlons all support a SMP standard better then Intel's.

I suspect that a linux implimentation of Athlon SMP will happen when boards are avaiable. AFAIK AMD is not hiding the specs.

Useless Review!

[KillRaven]

Why doesn't anybody do any worthwhile server reviews? I'm really not that interested in how well it handles compared to some Celeron in some multimedia benchmark. I want to know how it compares to Sun, SGI, IBM and Compaq Alpha hardware. I want to know how well it can serve up a couple of 100 remote X sessions or how it handles a 500 GB Database that get's hit heavliy 24 hours a day. This is essenitally a server set up, so why do they insist on testing it like they would test some crappy games box. Wow it's faster that a dual PIII 500, big deal, is it faster than a dual Alpha set up?

So while the test may have been somewhat entertaining it is completley useless. The benchmark isn't anything I recognise as an accurate simulation of a server environment and there are no real life tests. Show me a test comparing this to a Sun box running Oracle and 500GB of data and I might be interested.

Hello, 256K cache?

[be-fan]

Is it just me, or does Intel's new "use one die" for everything seem to have gotten them into a little trouble? I read the article, look for how exactly the new Xeon is different from a Coppermine PIII. Isn't the whole point of a Xeon the large full speed L2 cache? With the PIII having a 256K full speed cache, isn't a 256K Xeon, well, redundant? I do hope there are 2 meg integrated Xeons coming soon, because otherwise, you pay more for almost exactly the same processor.

Ugh.. Rambus....

[bildstorm]

Ok, PIII Xeons could be nice in a dual-processor setup, but why does Intel continue to insist on using that high latency RDRAM?

Tom's Hardware Guide just had an article which convinced me to stick with SDRAM for quite some time to come. Maybe for highly memory intensive long processes RDRAM is worth it, but how many of us will fin that worthwhile?

Re:Two Words For Ya!

[djohnsto]

First, I agree with post #36, 256KB is usually enough for an x86 CPU. Here is an explanation:

The reason Motorolla (and most RISC cpu's) need more cache is because code size is larger. The whole reason for CISC (x86 type) instructions is that they take up less memory. They do more work per instruction (this is another reason why MHz is a useless comparison between RISC and CISC). Since the code size is smaller, it stands to reason that they don't get as much benefit from a larger cache.

So, why doesn't Intel build larger caches and get just that much extra performance? Two reasons:
- it costs more
- large caches have more latency
It's the never ending battle in cache size to balance low latency with high hit rates. The more you increase one, the more you decrease the other. With full speed caches on x86, 256KB (with some set associativity) seems to be the sweetspot.

So, why use more cache on Xeon's? Applications that have many processes running and access lots of different areas of memory in a short time benefit the most from a high cache hit rate (bigger caches). This is exactly the type of application that servers run. In this case, the higher latency (slower) cache is worth having a higher hit rate.