Intel Cancels 800 MHz Xeon

goingware writes: "This article at C|Net tells how Intel canceled plans to produce an 800 MHz Xeon. They had feedback from major OEMs telling them they wanted fewer speedbumps with larger incremental improvements. I think that's a positive step, actually. I know from doing performance analysis of software that simply making a speedbump to a processor doesn't win the end-user that much, it's mainly for marketing reasons. This is because the performance of real systems these days is limited so much by memory access times and other factors. It would be better if manufacturers concentrated on engineering improvements that would result in real performance gains rather than notching up the clock speed."

Comments

Possible adverse effect on prices?

[Mr. Potato]

This seems to be a good thing for computer sellers, rather than computer buyers.

If the cpu speeds increase in less frequent steps, then the cpu prices will also decrease in less frequent steps (IMHO).

This seems more like an attempt by Intel to "throttle down" the market. Also it makes their marketing campaigns look better if they can demonstrate these artificially-contrived "big improvement steps". Which in turn leads to higher prices asked by Intel, for those big steps.

This seems to be a subtle money grab from the consumer...

It's the memory bus that really counts

[evilj]

It is interesting that mainframes, whilst having less CPU power than a Pentium, could still outperform them on IO-intensive tasks.

Nowadays, we have ultra-fast x86 CPUs, but chipsets that hold them back. I used to have a 486 motherboard that did memory interleaving to speed up memory accesses. I suppose when we had 70ns SIMMS it was more important, as well as cheaper to implement extra memory busses due to the lower pin count on a SIMM compared to a DIMM.

Anyway, it would make sense for the current x86 chipsets to have interleaving, although with SDRAM burst reads, it might be difficult to get the timing right. Maybe that's what has prevented it in commodity chipsets? Otherwise, I suppose you could have 4 byte interleaving thus:

DIMM0:hell
DIMM1:o wo
DIMM2:rld!
DIMM3:!!!!

You would still need some really low-latency memory in-between the main memory and the processor, and I guess the cost is another barrier to use in commodity chipsets.

It's interesting to note that the Alpha architecture has up to 8 times the memory bandwidth at 5.2GB/s than Athlon at 600MB/s or 12 times the Pentium at 400MB/s (although, an Alpha machine of such can cost $13,000) - check out http://www.microway.com/products /ws/alpha_21264.html for more in-depth information.

Enjoy,
J