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Transmeta Testing Mass Production
jackstaley sent us an article about Transmeta testing mass production of its Crusoe processor. They talk about IBM (which can make copper chips, but interestingly enough, has licensing deals with Intel that should protect Transmeta from potential lawsuits) as well as exporting the production to Taiwan.
From the article:
Big Blue also provides legal cover from Intel. Because of extensive cross-license agreements, only IBM and ST Microelectronics can manufacture Intel-clone chips for other designers and provide these designers complete legal immunity, said sources close to Intel.
However, from the crusoe tech page on the transmeta web site
The hardware component is a very simple, high-performance, low-power VLIW (Very Long Instruction Word) engine with an instruction set that bears no resemblance to that of x86 processors. Instead, it is the surrounding software layer that gives programs the impression that they are running on x86 hardware. This innovative software layer is called the Code Morphing software because it dynamically "morphs" (that is, translates) x86 instructions into the hardware engine's native instruction set.
So is it really a clone, or an emulator? I'm guessing Crusoe is just playing it safe
This is supposed to be great art. So why does it look like a bunch of decapitated naked people? -- Calvin
One of the demo's they had at unveling was a copy of DOOM, and x86 executable with part of the inner loop replaced by picoJava. It seemed to run that pretty quick, so it can switch instruction sets dyanmically. There is undoubtly some penality, but it apparently isn't huge.
There is no evidence that it can run Alpha code particurally fast. It has 48 (or 40?) registers internally. More then enough to do software registr renaming, and have operatinog regesters left when emulating a 4 register (10 if you count segment registes, the PC and flags) machine. The Alpha has 32 user visable registers (or is it 32int plus 32FP?). The 21264 has 80 renaming registers (invisable to the programmer) in two banks. The Crosue would have far less, so could be expected not to be able to hide as much latency.
Oh, and since the Crosue is designed to emulate the 32bit x86, it is not likely to have 64 bit registers, or a 64bit ALU. And it's FPU certonally is geared towards the x86 quirks (80 bits, almost IEEE, but not quite).
I wouldn't want to try to emulate the Alpha on a Crosue. It could probbably do a great 68000 (or the CPU32 in the palm, which is almost a 68000). Maybe even a good ARM, or V8 SPARC (these are pushing it though). Could definitly do a good JVM. Would do a great 6502, or Z80. :-)
But not a Alpha. Not a V9 SPARC. Not the 64bit MIPS. Not the IA64.