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0.01 Micron Process?
hypo writes "According to a recent ZDNet article, IBM is developing a technique called "V-Groove", that allows the channel lengths of transistors on chips to be 10 nanometers (0.01 micron) and below. Currently, most companies use a 0.18 micron or 180 nanometer process. This is certainly a giant leap. The only caveat is that IBM is not planning to use this in large chips (i.e., processors) for 10 to 15 years. However, this is still quite revolutionary because most people thought that a 0.02 process would be the fundamental minimum. This all shows that Moore's law can perhaps hold true in the future. This article also discusses Carbon Nanotubes, which might research market faster than experts had previously thought."
Someone please correct me if I'm wrong (I certainly might be.. I'm not intimately familar with microelectronics engineering), but I thought what we currently associate with chip die processes are the trace widths, not the channel length.
Trace width is the width of the conductors connecting different transisitors on the chip. This is important because a smaller trace width means that the whole chip is scaled down, including the spaces between the traces. This raises capacitance between parallel wires and causes the posibility of cross-talk.
As for channel length, the article says:
Channel length represents the distance electricity needs to travel through a transistor, shorter transistors lessen the distance traveled, delivering greater performance.
While this is related to performance (specificly, switching timings), I am not sure if it is related to trace width at all. The ZDNet article may be mistakenly associating the two.
Also, I think that one may be able to vary the trace width and the channel lengths independently. If that is the case, we may have performance increases from channel lengths even if we hit a wall when it comes to trace widths.
Can someone with some microelectronic background clarify these issues?
Thanks.
Using your sig line to advertise for friends is lame.
I work for a silicon wafer manufacturer, we supply Intel, AMD, etc with the wafers that they put the chips onto.
.13 micron. The human eye can only see down to .30 microns or so. (That's under ideal conditions, dark room, 200 watt halogen light focused on the wafer.) Needless to say there has been a transition to machine only inspection as the chip lines widths have gotten smaller.
.13 micron line widths makes me wonder what the yields will be like. The machines that can see down to .13 micron run about 1/2 million or so. I haven't seen what the next generation of them will do, but I know that we don't have them installed in our plant yet. That is definately one reason why it takes so long for this stuff to reach consumers. The clean rooms that the wafers are cleaned and inspected in are filtered down to class 10, which translates to less than 10 particles in the air at .3 microns. We usually have 0-1 at .1 microns. Makes an operating room look positively filthy.
The wafers we supply have and 'Epi' layer on them, which is short for epitaxial. The layer is silicon that is grown on the wafer at a high tempurature (I think 950-1000 degrees C). This makes the wafers less rough, thus smaller lines widths. The wafers are inspected for defects, and the machines that inspect them can only see particles, pits, etc down to
Intel already annoucing the
The wafer manufacturers are mostly breaking even at this point. Intel is making fat cash, but they are getting it from squeezing all the wafer suppliers. Some have dropped out of the business do to the lean conditions. Nobody really has enough money to buy equipment to make these wafers on a large scale, let only finding vendors that have equipment that meets those specs.
.01 micron, holy crap!
They haven't even made a chip yet! They have just made a transistor or two.
It is not even clear from the article how small they have gotten the channels: it only says that the technique "scales to" 10nm.
There is a long way from showing that a given technology will sort-of-work in a lab to mass-production. That's one of the reasons for the delay.
Another is that there might not be a market. It is currently quite feasible to get a couple of ~1GHz processors with a few gigs of RAM in a machin we can almost afford. Let's face it: few of us sitting here reading Slashdot are using our quad-Xeon workstations to their fullest. Who would really buy it at, say, 100 times the current price? I've just ordered my dual-PIII and I doubt I could easily use more processor speed. (Memory, maybe.) And I'm sure I wouldn't pay half a million bucks for it!
Hi!
I have one question here: will software really need more and more CPU performance as time goes by?
I mean, as the article says, sure, servers and stuff will definitely put good use to the increase in performance, but what about good ol' Joe Sixpack using Excel at his office? I mean, besides from cranking SETI@home units faster, is there really such a need for faster processors at home / office?
In all honestly, I stopped noticing any speed differences around 200MHz or so. I used a 200MHz Pentium running Win NT for a while at work, then I went to a 400MHz Pentium II. Couldn't tell the difference at all.
It is getting to where rewriting software and/or changing your approach are much more valuable than processor pissing contests. When I compile code with Visual C++ it seems to take forever, given a large project. If I use Object Pascal instead, the compilation time drops by 2-3 orders of magnitude. That's a much bigger win than increasing my machine to a 2GHz processor.
Maybe with this tech 3dfx can make a voodoo5 small enough to fit inside my computer case.. :)
>Or would it be impractical or inefficient to do that?
Yes, and yes. At least, for a while.
By the sounds of the article, they've only managed to create a handful of transistors using this new process. All a transistor consists of is 3 layers of semiconductor with interconnects -- not a particularly complex structure. The next phase will be building a non-trivial circuit. This, no doubt, will require reworking of their technique (read: years of research) to produce an experimental prototype. Then comes tuning to actually make it useful. At this point, they're still basically producing the chips "by hand" -- very expensive and time consuming with a very low yields.
Once they've proven that the process really does work (assuming, of course, that it does), and that you could conceivably build a real chip with it, they need to design the mass production fabrication hardware. When that's done, they'll actually be able to turn out a few chips, as you said, on a smaller scale -- no doubt still at tremendous cost.
The last barrier is the infrastructure. The final version of the new process will likely require overhauling one or more existing FABs (or building a new one), again at huge cost, both money and time.
10 years from single transistor demo to the first production model is actually pretty quick. It's the same story again for other innovations -- be it faster/smaller chips, higher density hard disks, holographic storage, whatever. The more radical the new strategy, the longer it takes to get it right and get it ready.
Drinking will help us plan!
If you go any smaller, your waves become X-rays and that significantly complicates matters.
--
With chips like this, we can fear only one thing: the marketing campaign. Intel's was bad enough, even without a name like V-Groove.
--Jeff
10 to 15 years is the time frame for them to get machines that can make these paths on a large (30-60 million transistor) scale, plus the time for them to build enough of said machines to actually be able to produce enough of these chips for people to care (if you can't buy it, then who cares how fast it goes), plus then the time for them to build a plant to house these machines, plus the time (after that) of installing the machines and doing test runs. There are all sorts of stuff that it's easy to do a couple of times, but it gets hard when you're expected to do it a couple billion times.