Reconfigurable Computers - Again?
shermNOTsherm writes "Here's a story on UniSci about research at the University of Rochester on reconfigurable computers. The idea is to dynamically adjust cache sizes on the fly to more efficiently operate. Supposedly halves power consumption, and is based on current commercial chips, not customized, so it's just a little closer to real world."
Amen, brother! Remember the mid-80s? Full-GUI multitasking micros with 1 MB of RAM that could boot in (I am not making this up) under 2 seconds. My home computer now has over 300 times the RAM, 50 times the MHz, and 9,000 times the disk storage. Yet, amazingly, it takes 100 times as long to boot, and (apart from games) delivers very little in the way of application functionality that my system of 13 years ago did not. My OS alone requires what would have been 40 hard drives and 256 times the maximum possible RAM of the computer on which Unix was invented, and cannot support two users. This is progress?
One problem that I suspect this particular technology will suffer from is that modern preemptive multitasking operating systems in combination with object orientated code (which suffers from poor locality, unfortunately) mean that any microcode designed to detect low levels of cache usage etc isn't going to have enough time to respond before either the OS does a context switch, or the working set of the executing task shifts.
Having said that, I firmly believe that both this technology and Transmeta's 'codemorphing' ideas will become the norm within the next few years. Now, if only they could JIT Java bytecode in microcode...
So, it's having a chip that can turn off parts of itself when they aren't needed. Lots of processors today do that. Lots of processors change their speeds to cut power as well. They don't cut their cache sizes though, which this is proposing. It makes sense though - the cache has to be on all the time to keep from losing data, but why couldn't you get about the same effect with today's processors by making them flush their caches and power them off when going into a low power state? Of course, this technology would allow you to work at the same time, at a lower speed, but the full power on time of a microprocessor today is measured in nanoseconds - you wouldn't even notice it. Loading from memory may take a bit longer, but it's still not noticeable, except in artificial tests.
As for the speed increase aspect of it, I doubt that this tech can turn L1 and L2 caches into each other - it probably can just cut the sizes of each - so leaving them all the way on all the time would give you them best performance - and of the power saving features would at best change nothing.
Sounds like a neat idea though, but the proof will be in the implementation .
Lets face it; a lot of commercial software out there is bloatware of the finest. Recently I did a small test with some friends who also had a laptop; pentium 160Mhz, 64Mb internal memory, 4Gb harddisk, 12.x" LCD screen and running Windows 95. My laptop is a PIII 550Mhz, Win98, 6Gb hardisk and has a 14" TFT screen. Both were equiped with a PCMCIA network card. We put the laptops next to each other and booted the machines. The 95 machine was waay done while mine was just past the PCMCI initialization. And no; my machine does not have major programs which are loaded during boot; its a very plain Win98 installation, most commonly used for office applications and demonstration purposes.
Second example is something which most people experienced afaik; if you take win98 running on a PII266 Mhz and on a PIII500 Mhz you will notice some increase in performance but not as drastic as it could be. If you compare all these Windows based experiences with an environment as Linux, BeOS or OS/2 (I haven't played around with BSD myself) then you'll notice that by using environments like Windows you don't use the hardware to its full capabilities.
Offcourse I do realize that this isn't an issue in all cases. Not everyone uses Windows and in some environments the software is allready at the 'cutting edge' in which there is no more performance to gain by adjusting the software.
But if you focus on the consumers market then the remark "We'll have to rely on innovations like this to go faster" is not the issue.
Mobile processors have been disabling their caches while in low-power mode for 5 or more years.
The only thing remotely new is that they are only disabling part of the cache at once, instead of the entire cache. Then again, that's probably enough for a patent these days...
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