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Is IBM's Power4 A Threat To Alpha, Sparc, IA-64?
HiyaPower writes: "There is an interesting discussion here about the IBM
Power4 chip. While it is most directly compared with the upcoming Alpha, it also has ramifications for the penetration of the IA-64 and/or Sledgehammer into the server market. Conclusion drawn is that the Alpha, etc., may be in for some very tough sledding. Now if only Apple could be persuaded to use these instead of what the article terms its "embedded controller chips...""
The article says POWER4 implements the 64-bit PPC ISA. Does that mean it could run current PPC binaries with no problems? If so, Apple could drop it in to future Macs with nothing more than some changes to the kernel...
Jobs has got to be pretty pissed at Motorola by now. Rumour has it he's shopping around for new chips. I bet AltiVec is the only thing holding him back. AltiVec is truly amazing for certain tasks...
Is there a technical reason why IBM is avoiding AltiVec? Could AltiVec somehow be responsible for the problems Motorola is having boosting PPC clock speed?
Oh, and can you imagine a Beowulf cluster of these? Sorry, just had to say it. It would be pretty mind-blowing, wouldn't it?
If Linux on PPC is a key part of their strategy, it would be nice if they threw some support to open source compiler optimizations for PPC. It'd be a shame to have Linux underperforming on these puppies because the optimizer was not everything it could be.
Post may contain irony: discontinue use if experiencing mood swings, nausea or elevated blood pressure.
Since UNIX supported 32 bits in 1979 (VAX) and
it took MicroSoft until Windows 95,
I hope they are faster this time around!
An over clocked micro-sequencer could have the same effect without the problems of pipeline refilling at a branch. Overall, I suspect the over clocked sequencer approach might offer comparable performance with a much quicker design cycle - and or - lower design cost.
Bzzt. Wrong answer.
Granted, S/390 is not the most popular hardware for ISP's, plenty use S/390. Here's an article about one.
Here's an article where ebay discsses the possibility of moving to the S/390 platform.
This article discusses how some government agencies are web-enabling their mainframes.
I'll grant that traditionally IBM mainframes can be a bear from the usability perspective. However, things are changing quite quickly, especially with the advent of Linux on the S/390.
have a day,
-l
In the long run, we all know that what will count is OS support. IBM has a strong, stated linux strategy, but we'll see where it goes.
Don't get me wrong, I am one of the few who actually like AIX. I think it's a mature, useful operating system with some really cool characteristics (fairly integrated hw support and debugging, excellent logical volume manager (better than veritas, imho)). nevertheless, it remains to be be seen whether IBM can actually bring Linux to their whole server platform (including these bad boys).
(There have been instruction set changes in the IBM processor line in the past, particularly between the POWER, POWER2 and POWER3 architectures, so I'm interested to see what the differences in this instruction set are...).
To IBM's credit, myself and some geek friends were at a smallish local tech convention and some IBM guys were there talking about their new nomenclature and such in their server lines. For the really big stuff, the S-390's ( I think pSeries and zSeries but I could be wrong) they run stuff that handles HUGE, HUGE payloads ... run AIX ...(isn't there OS-390 too) but for their middle range stuff, we couldn't get the guys to shut up about Linux. One of our guys mentioned it and the talk was all about that the whole time. "Our customers like it because we don't have to package costly licenses. And it's very, very, very scalable and flexible, we can run it on everything. And it's a UNIX so we can integrate it with AIX ... " on and on...
So just for that IBM's not a bit bad, and their NUMA-Q architecture looks REALLY neato. As for putting Alpha and Sparc out of business...Hey, you build a better mousetrap. Big Blue has always had great R&D and put out some of the best products out there. That doesn't mean Alpha and Sparc and such are going to plummet.
I say kudos to Big Blue.
Angry IT woman in big clompy boots. And talking lint!.
- MM5 is a big sloppy vectorish code for meteorology modeling; POWER3 delivers about 25% of the performance I would have expected from its LINPACK numbers and given MM5 benchmark performance on known SGI's and Alphas.
- MAQSIP is a big air quality modeling code highly optimized for general microprocessor/parallel; POWER3 delivers about half the expected performance.
Does POWER4 have a similar gap between performance on a very simple and regular app (LINPACK) and real-world ones ??NOTE: for what it's worth, Sun SPARCs give excellent MAQSIP performance, but even more miserable MM5 performance (as compared to processor-peak) than POWER3.
"My opinions are my own, and I've got *lots* of them!"
"[...]no unix server can currently compete with even a middle of the road OS/390 machine for heavy server/transaction/database type workloads."
This would be true if you added "in a ultra-high-reliabilty environment". Fact is that not a single ISP uses S/390 systems for serving web content. If the IO of these machines would be so excellent, why don't they use them? What makes things even worse is the fact that serving web pages is similar to the IO load envisioned by Amdahl, namely relativly large chunks of data being tranfered. As a result even the terminals (3270) are based on transactions of this type. The user edits on the screen and commits changes every once in a while. This is very different to the character based aproach of Unix ttys.
"[...]a modern OS/390 the IO is handled by up to 1024 of these processers called 'channels'."
This is unclear to me. OS/390 is an operating system but you seem to make a statement about hardware. True is that 390-IO is based on a channel subsystem. All models from G3 through G7 (GA 2000) have 256 channels. Wrong is that a channel has something to do with a processor. A channel is an IO line with an interrupt on its own. Each of these channels may end in a channel controller. To the channel controller one can attach 256 subchannels. The subchannels end in a device. This makes a total of 64k devices.
A modern G6 has 16 processors (390 architecture). 14 for workload, 2 for the IO subsystem, 2 in case two of the others die.
"Nearly everything relating to transactions was done forst on an OS/390, databases in general, relational databases, messageing and queueing software, & etc. are all areas where the intial and continuing innovation took place on OS/390s"
True. One of the last "innovations" of DB2 on 390 was to optimize the data distribution on the harddisks depending on the speed of the movement of the HD heads. The last 390 harddisk physically built was a 4 Gig drive (I beleave it was called 3390 model 4) in the early 1980s. The disks had a diameter of almost 1 yard. Since then IBM simulated these 3390s through (SCSI-) disk arrays. The controlling software of these RAIDs introduce special waits to not disturb and crash DB2 that relies on specific timings.
The last disk logically defined was a 8 Gig drive. In case all 64k devices are 8 Gig drives this makes 512 TB storage. This will be a boarder very difficult to cross.
Is OS/390 innovative? All I know is that the OS/390 filesystem is non-hierarachical, i.e. does not know of directories! The filesystem is not block oriented. If you append data to the end of a file the file may overflow. This means that the user must create a new, bigger file and copy the old file into the new one and delete the old one.
Programs in OS/390 must be started using a special "scripting" language to supply parameters!
I could go on with this list. 390 were nice in the 70es. They still do a good job in some places that can afford them and need high reliability. All I'm saying is that the future belongs to a different kind of machine (definitly not 31bit like S/390) with a different kind of OS.
IBM politics was that certain techniques (like the ceramic multi-chip modules, copper process, etc.) were reserved for the S/390s. This was the reason why the RS/6000s with AIX were never really competitive (S/70 AIX server).
When SUN brought their E10000 server into shops IBM thought they'd never loose to SUN they obviously started changing their minds. The (RS/6000 based) 24 processor S/80 outperformes the 64 processor E10000.
This new POWER4 design makes clear that IBM favours modern Unix-based RISC servers over the old S/390 mainframes.
This is a good thing especially for IBM S/390 customer who start having problems finding talented people who want to work with dinosaur machines and OSes. (IBM also has major problems implementing new or even innovative software for the S/390s. Exception: Linux/390 ;-).
Better IBM offers them a safe way into the RISC/Unix world (we are looking at huge amounts of enterprise critical data sitting on all these S/390s) than when they try to migrate on their own.
I have to wonder if an over clocked microprogram unit with a CISC instruction set couldn't be made competitive again. Ultimately that might be a simpler design - and thus potentially faster than a modern RISC chip.
One of the ultimate limits on processor performance is how fast you can get instructions into the processor. If you think of CISC as a compressed (Huffman encoded) version of RISC it is easy to see that CISC does have a theoretical advantage there.
I know this is heresy, and that the modern religion is RISC == GOOD, CISC == BAD; but it might at least be worth someone spending some time thinking about it. If nothing else, the reduced transistor count could do something about the spiraling power consumption problems in processors. Or you could integrate multiple processors on one die and do the SMP on chip with the much smaller cores this would make possible.
According to Robert Morgan who runs Apple Recon
Steve Jobs said in a visit to Motorola
"It will be great in two years when we arn't using your chips."
After this statement is when Motorola publicly started calling the PPC line 'embedded'
How often in YOUR relationships can you walk up to your relationship partners and tell them 'to hell with you, I'll be leaving in 2 years.' and NOT expect said partner to keep giving a damn about you.
Apple then made the problem WORSE by pubically calling altivec 'the future' and spent hours about how wonderful altivec is. Apple will have a hard time leaving AltiVec with all the statements about how wonderful altivec is.
Jobs ego put Apple in the place Apple is. Motorola only reacted to the actions Jobs took. It is not like Motorola NEEDS Apple, and took actions to protect Motorola's investment.
Jobs wants to be the 'saviour' of Apple, fine. Then Jobs must also take the mantle of the person who helps kill Apple also. Amazing how the history of Jobs repeats.
If it was said on slashdot, it MUST be true!
That line first appeared with the 386. And it was wrong then, too.
What servers really need is multiple CPUs and huge I/O bandwidth, not faster individual CPUs. Loaded servers always have lots of threads running. On desktops, one thread typically is using most of the CPU time. Thus, the desktop is the place where the fastest CPUs are used. Servers are configured for max price/performance without sacrificing reliability, and tend to run a bit behind the fastest desktops.
On the other hand, Apple can't afford to change CPUs again. The last transition cost them a big fraction of their applications (for example, almost all the CAD vendors bailed out) and a big chunk of their user base. In retrospect, better 680x0 machines would have worked out better than going to PowerPC. The whole PowerPC thing was supposed to get IBM into MacOS, remember, and that was a total disaster. Now that everybody knows how to make CISC machines faster, there's no reason 68K machines couldn't be up there with x86 machines. And the architecture is much better.
1GHz Power4 beats the crap out of a 500MHz G4 w/AltiVec. I don't care *what* you're trying to accomplish.
These are my friends, See how they glisten. See this one shine, how he smiles in the light.
I think the big advantage that VLIW instruction sets will have is strictly architectural, and I'm not sure how IBM's approach fits in yet, but it looks interesting. Throwing more chips at the problem is one approach, but remember that your competitors can do that too, *and* make the chips do more as well...
Not sure how IBM's approach fits in yet?? Read the article.
Amongst other things, the POWER4 is *not* VLIW, it's straight-ahead modern RISC at its finest. With massively gigantic buffers, bandwidth and execution resources (8 functional units/core * 8 cores = wow), this chip'll do quite nicely on IPC/core, not to mention combined IPC for all 8. While presumably not quite as elegant, the design for the individual cores bears a lot in common with the archetype of perfect RISC cores, the Alpha 21264, and it has even more aggressive resources.
Essentially what this means is, assuming this design is as good as it appears, the only way the competition will be able to catch up (without going the way IBM has and deciding on a prohibitively expensive 8-in-one design and packaging) will be through the use of innovative design tricks. The upcoming P4 has a few of those, incidentally, but the big one--and the one the P4 *doesn't* have--appears to be SMT, Simultaneous MultiThreading. Alpha has an 8-way SMT core coming out in a bit, and it ought to compete well with IBM's much more expensive 8-way SMP design here. And AMD appears ready to do 2-way SMT (or something similar) with the Sledgehammer in about 15-18 months. And Sun is rumored to have SMT in the USV design due in several years. But the POWER4 looks to lead in the "big bad" category for quite some time to come.
(As for Intel's EPIC, the VLIW-like design strategy for their IA-64 chips, at the moment it's looking like a rather poor competitor to SMT. A quick explanation of why:
There are exactly two ways to make an MPU run faster: 1) increase the clock speed, or 2) increase the IPC (instructions per clock). Unfortunately, the best we've been able to do so far in the IPC realm is about 1.4 IPC on SPEC benchmarks (Alpha EV6x). IPC on a P3 runs about 40% lower. Now, these IPC numbers are despite the fact that the Alpha can theoretically retire 8 instructions/clock, and the P3 5 (5 internal ops, not 5 x86 ops). Furthermore, simulations show that as far as attacking the IPC problem by adding more functional units, we're nearing the point of diminishing returns.
The problem is, in order to run lots of instructions in parallel, you have to be able to safely extract parallelism from your code. And the problem with this is, you can't run instructions in parallel if they have dependencies, etc. And furthermore, nowadays all this parallelism has to be safely extracted in real-time by special hardware in the MPU itself; this makes your chip more complicated, and means you need to build a big buffer to hold instructions in flight so you can pick and choose which ones you want to run each clock.
So many many years ago, HP had the idea, which it later sold to Intel (and which wasn't really there idea at all but has indeed been used in DSP chips for years and years), of getting rid of all that complex insruction-level parallel-finding logic on the MPU and doing it all at compile-time instead. This is the basic idea behind EPIC, the philosophy of Intel's IA-64 line.
It sounds very nice, especially because in theory it means simpler chips (no complicated control logic), and simpler chips means faster chips. Heh heh heh. See it turns out that the amount of instruction-level parallelism which can be safely discovered at compile-time is way way less than the amount that could be found in the chip at run-time (which, as we recall, is too small already). Thus EPIC was modified to allow the compiler to just place "hints" in the code. Well, this means you still need all that complicated control logic back in place, because you still don't have deterministically scheduled instructions. But following the "hints" and other changes to the ISA ends up making everything *more* complicated, not less. This, in a nutshell, is why Itanium is 3 years late, way over budget, unable to meet its very modest clock speed goal of 800 MHz, and fitted with a laugh-enducing 96kb of on-die cache, lower even than the lowliest Celeron: all this added complexity means bigger, slower, more complicated chips that don't have the room for cache or the elegance for high (or even adequate) clock speeds. Plus we have very strong evidence that compiler technology is still not nearly good enough to make the kinds of insightful IPC-giving "hints" which are necessary to even make the damn fool scheme work. Thus the only benchmark Intel has "released" for the Itanium is that of an RSA-encryption--a routine simple enough to be hand-tuned in assembly. Meanwhile they have made the patently ridiculous claim that the SPEC benchmarks--directed precisely at the mid-cost server/workstation market which Itanium is aiming for--are "not relevant" to Itanium's market.
A completely opposite approach is SMT, which uses a relatively small number of core changes to allow not just instruction-level parallelism to be gleaned, but also thread-level parallelism. In other words, the chip will run several threads in parallel, confident in the fact that their instructions will not have dependencies on each other, and thus be able to use much more of its full execution capabilities. Early indications are that SMT can improve IPC by remarkable amounts, like on the order of 2x the performance on otherwise similar cores!
Unfortunately, it is too early to tell whether SMT will be as easy a design enhancement as is being claimed. Furthermore I've heard tell that SMT on IA-64 will be a lot more difficult than on a RISC MPU, so Intel could be missing out on a huge speed-up with this technique.)
However, IBM will have to make sure people design their apps with more than one processor in mind, which will be a Good Idea for the future, since more people might have multiprocessor computers.
These chips are not to be confused with PowerPC chips. They are server chips only, intended for seriously expensive machines.
- running Quake 3 Arena
- overclocking these babies
- A Beowulf cluster of these
Hardly a "discussion" IMHO.I know MOSR is not the most reliable of all sources (they were right about the cube though) but a few months ago they put up a rumors about Apple and IBM trying to get the Power4 to work in Apple's UMA-2. The rumor also had a pretty good link to some info on the Power4 chip. The link gives you a PDF that cover some of the same material in the article of this story but it is still worth a look.
p ower4.html
The rumor is now archived at:
http://macosrumors.com/?view=archive/8-00
If you dont feel like going to MOSR the link in the rumor to the Power4 info is:
http://www.austin.ibm.com/resource/features/1999/
Now we've gone full circle and memory is the bottleneck again. CISC could provide a performance advantage again.
Also, I hope not.
Hey, this chipset is for some serious computing. Serious, serious. The range of boring, mundane software that would get a big boost from these fat, fat pipes into these fast, fast cores is limited.
Quake]|[ would absolutely drip with 3D VR gore. (I get ill just thinking about it. Gibs everywhere!)
But would you really need that kind of horsepower to run Word or an Excel spread sheet of even the maximal complexity that Excel can handle? I thought not. (Excel plays fast and loose with some math functions, Newton's approximations, etc. I just implemented algorithms which don't. Banks can't use Excel for real world amounts.)
Face it, M$ can't use it. Even GHz x86 chipsets are a waste for the desktop.
The server market is better served by Unix solutions that runs multi-user(NT is not), multi-threaded,) and across a range of big iron that's growing steadily bigger.
M$ support this? I hope the [expletive deleted] not!
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The article is very strong, but it would have been enhanced if it also touched on AMD's upcoming 64-bit offerings, the Hammer family of chips.
Hammer does not have a track record in the marketplace, but neither does Itanium, and it's odd to ignore an architecture that in all likelihood will sell in much greater volume than several of the chips profiled here. Even if AMD's 64-bit implementation turns out less than ideal, it will probably outsell the Power, Alpha and Sparc offerings by virtue of the vastly larger market it targets.
A simulator for a Hammer chip has been released. A comparison, or at least an acknowledgement, would have made the article more valuable.
Tastes Like Chicken
That said, I don't what Motorola's plans for a G5 are, if any. It may turn out that Apple has no choice but to go with IBM's chips after a while.
Free Hans!
PPC chips are optimized for cost, POWER chips are optimized for performance, screw the cost.
Mea navis aericumbens anguillis abundat
Microsoft's OS dominance is limited to low-end desktop systems. In the server arena they are but one player among many.
Lee Reynolds
Muslim community leaders warn of backlash from tomorrow morning's terrorist attack.
Alphas are not dead. A few days ago, Compaq had a major deal with Ericsson to supply them with Alpha processors for Ericsson's upcoming AXE switchboards.
Imagine, embedded Alphas!
As this is a major deal, Compaq will have an output for years to come and the Alphas seem far from dead, or even threated.
Sadly, i have to go offline for a while, Not ignoring anybody, just not here. Sorry.
On The Other Hand, Apple's direction has lately been to using convection cooling, not the water cooling that would be necessary for the number of watts the Power4 dissipates.
If you're not part of the solution, you're part of the precipitate.
Heh! If only Apple would use these, the new iMacs wouldn't exactly be quite able to hit their price points. Paul (the author of the article) and some others were involved in a thread over on the tech forum at Ace's about (amongst other things) the expected cost of one of these puppies.
To quote Paul's response:
Maybe another way of looking at it is perhaps the price of four POWER4 known good die and the ceramic substrate and metal carrier totals $3000 (although I suspect that a tested and 100% functional ceramic substrate itself might approach or exceed $3000 in cost).
The real question is the cost of a fully assembled and tested, 100% functional, POWER4 8-way module? After all what are the chances one of these can be reworked if even just one of the 20,000+ solder ball joints was bad?
So for one of these 8-way on a chip jobs (unsure if they'll be offering 4-way configurations too or if those were just a prototype) it's looking like upwards of $10,000 just for IBM to fab, package, and test the darn things. Add in a system capable of feeding it the tremendous bandwidth it requires to run up to its full potential--8 GB/s to DRAM and a phenomenal 84 (!) GB/s I/O--and...ok, so I know Hemos was just joking when he made that comment about Apple, but you get the idea. These are MPUs you use to fold proteins and run gigantic dynamic-content websites, not surf the web and edit the home video of your kid's elementary school graduation.
On a related note, man these things oughtta show Intel a thing or two about how to marry clever instruction scheduling to brute-force functional units--forget about Itanium; it's gonna take a several-way McKinley system to even take a swing at this these. And it oughtta show Sun a thing or two about the dangers of resting on the laurels of your marketing success when designing new chips. And, as Paul notes in the article, it really oughtta make Alpha engineers worry that for the first time, having the most elegant design may not guarantee the best performance. Compaq has an 8-way SMT Alpha core on the way as well (EV8); too bad the Alpha group's customary position in the world--stepped on and neglected by their corporate masters--means they haven't got the money or manpower to bring it to market until well after POWER4.