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Diagonal Design For Chips

Posted by Hemos on from the seeing-things-at-an-angle dept.

A reader writes "Simplex and Toshiba have a new design tool that allows circuits to run on diagonals. They're calling it X Architecture. Applied Materials, KLA-Tencor and DuPont Photomasks have signed on according to the press release. They're claiming 20% less 'wire', 10% faster, 20% less power and 30% better yields. Here's an EET article."

5 of 81 comments (clear)

  1. Hardly a Breakthrough by HardCase · · Score: 5
    Sure, it's a good idea...a straight line beats a 90 degree angle most of the time, but I think that the real breakthrough in this case is the potential for Simplex to make a lot of money in licensing fees to radically redesign the tools that we use to design and manufacture chips.

    Since the architecture isn't going to change on the top layers, where most of the action is, the improvements become incremental. It would be nice, though, to be able to shorten long interconnect runs, especially with capacitance becoming a significant issue now. But I wonder if the significant cost to replace existing design and manufacturing tools is worth the seemingly small gains that the technology offers.

    -h-

  2. I'm somewhat skeptical by taniwha · · Score: 5
    Their press release claims they comtinue with normal style routing on M1-M3 (so people can continue to use their existing cell libraries - this means that the raw gates will NOT run any faster - gate layout is usually done in M1 and a bit of M2 and the silicon below). What they are proposing is a better long wire routing (it seems they rotate the M4/M5 grid by 45 degrees - and that's what those upper layers are usually used for) which is a good thing since wire loads are what's currently killing us in timing - theorretically (best case) you can get a sqrt(2) drop in R and another in C (for a product of 2x speed up in wire delays) when you replace 2 wires with their diagonal - not all wires are going to be perfect 45 degree replacements. Also I suspect there's asome problems with getting the 2 grids to line up - I bet there are limitations on where vias can poke thru.

    What I am skeptical about is that it means a whole new routing infrastructure - not just new routing tools (which I guess is what they are really selling) but also 3d extraction tools, timing infrastructure, DRC etc etc getting all of this working from all the different vendors and getting it to work together is NOT going to be easy

  3. Just an Interconnection change... by Orne · · Score: 4
    When I first saw the title, I saw "diagonal" chips, and in my mind, I imagined layers of silicon wafers stacked in 3D like //// with interconnections between layers running \\\\.

    But no, all they did was decide that instead of the time-tested grid format, we'll just run our interconnection wires 45 degrees diagonally accross the chip, but still pretend there are grid "nodes" for automation purposes. (for those not in the know, interconnect are the higher-level wiring that connects "blocks" of circuits together, such as connecting adders to multiplexers)

    Building 3D layered chips is a whole 'nother beast.

    Just remember, they're only saving wiring only at corner-type junctions, and even then, only what can be optimized to fit within the existing wiring mesh. Still, saving wiring is a big improvement; as we should all know, excess wiring causes heat, voltage, and frequency problems (due to line charging effects). On the other hand, most modern toolkits are written to optimize to a 2-D grid, not to mention most modern lithograph manufacturing tools. But, thats the point of the "discovery".

    -- Scott
    ... who should be working

  4. 10% is a breakthrough? by mblase · · Score: 4

    A perfectly obvious way to shorten wire lengths using basic geometry, resuling in a mere 10% improvement in performance, qualifies as "a semiconductor breakthrough as significant as copper interconnects"?

    According to Moore's Law, I could have gotten the same improvement simply by postponing my purchase for two months.

  5. What about Cooling ? by Rosco+P.+Coltrane · · Score: 4
    Don't they run into cooling issues if they have a method to cram more transistors/cells into a given volume ?

    My understanding is that modern processors use diamond to conduct heat outside the processor core : did they also create an orthogonal diamond layer to conduct the heat out ?

    --
    "A door is what a dog is perpetually on the wrong side of" - Ogden Nash