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Itanium Update
NegaMaxAlphaBeta writes: "For those of you interested in Intel's Itanium 64 bit processor, EETimes has a nice update article to let us know what's happening with this beast. With an 8 stage pipeline, as opposed to the 20 stage pipeline in the P4, clock frequencies are obviously not as high (~1 GHz). Other notable numbers extracted from the article: 130 Watts power consumption, 328 registers, 6 MB of onchip L3 cache ... quite nice (well, not the power thing). I'm sure many people can appreciate 64 bit integer ops; for me, it means single instruction xor for the 64 bit hash codes used in chess transposition tables."
So when most people go out and buy a computer, they see a lot of mhz and think it's really fast. So if they're use to 2ghz+ pentiums, why would they even think of buying a 1ghz itanium? Sure, I know it'll probably be faster, but how does intel plan to market these? Will they also drop mhz ratings like AMD? Or will they go on some major re-educaiton campaign, like Apple?
F-bacher
James Tiberius Kirk: "Spock, the women on your planet are logical. No other planet in the galaxy can make that claim."
I hope that in the future people will read about morons like you in the history books and shake their heads at your willful stupidity in the face of overwhelming evidence.
Funny how identical code
; 6 : for(i=0;i<10;i++) j+=1;
00006 c7 45 fc 00 00
00 00 mov DWORD PTR _i$[ebp], 0
0000d eb 09 jmp SHORT $L468
$L469:
0000f 8b 45 fc mov eax, DWORD PTR _i$[ebp]
00012 83 c0 01 add eax, 1
00015 89 45 fc mov DWORD PTR _i$[ebp], eax
$L468:
00018 83 7d fc 0a cmp DWORD PTR _i$[ebp], 10 ; 0000000aH
0001c 7d 0b jge SHORT $L470
0001e 8b 4d f8 mov ecx, DWORD PTR _j$[ebp]
00021 83 c1 01 add ecx, 1
00024 89 4d f8 mov DWORD PTR _j$[ebp], ecx
00027 eb e6 jmp SHORT $L469
$L470:
; 7 : for(i=0;i<10;++i) j+=1;
00029 c7 45 fc 00 00
00 00 mov DWORD PTR _i$[ebp], 0
00030 eb 09 jmp SHORT $L471
$L472:
00032 8b 55 fc mov edx, DWORD PTR _i$[ebp]
00035 83 c2 01 add edx, 1
00038 89 55 fc mov DWORD PTR _i$[ebp], edx
$L471:
0003b 83 7d fc 0a cmp DWORD PTR _i$[ebp], 10 ; 0000000aH
0003f 7d 0b jge SHORT $L473
00041 8b 45 f8 mov eax, DWORD PTR _j$[ebp]
00044 83 c0 01 add eax, 1
00047 89 45 f8 mov DWORD PTR _j$[ebp], eax
0004a eb e6 jmp SHORT $L472
$L473:
is less efficient. Perhaps you need to get a decent compiler.
My god. I'll never learn assembly on a modern chip. I tried on the 386/486, but gave up, and opted for the 65c02 (a fine little chip). I'm getting to the point where it's time to move on, and I was going to attempt the 68k or even PPC (no altivec though). I think I might actually manage to learn that, but I can't even begin to imagine 328 registers. Especially arranged the way intel tends to arrange them...
Will anyone outside of cpu engineers and compiler authors even learn asm on this monster? Or have we truly moved past the point where programmers understand the cpu?
328 *physical* registers, not logical (ISA accessible). with 128 context switches will hurt big time ia64. yet another bad design decision of the itanic.
A context switch happens one in a blue moon. Fast context switches are not going to make up for sluggish performance for the real work the machine is doing between context switchs. Registers are considerably faster than cache; the absolutely fastest cache in the world is P4's L1 cache which has a load latency of 2 cycles, and on most architectures it is 3 cycles. Putting 128 qwords into registers is an absolutely dramatic speedup for programs which have a working set more than 8 dwords (all that IA-32 gives you).
I think I've figured out what the whole 64-bit thing is about. It means that each instruction (right term?) has more capacity to carry data. This doesn't necessarily mean that it will be twice as fast, of course, because not all instructions are that large.
What I'm confused about is how it affects programming. Does this mean that everything will need to be optimized for you to take advantage of the higher bitrate? How will programs that are written for 32-bit systems handle it; can they handle it? How about backwards compaibility?
Do any other people read these sort of threads even though they know that it will be over their heads most of the time?
--Kintara
I received this from one of my intel comrades which was sent to all of the intel eployees.
Speed is important. On Monday, Intel launched the Intel® Pentium® 4 processor at 2 GHz. Tuesday, during his keynote atthe Intel Developer Forum, Paul Otellini, executive vice president and general manager, Intel Architecture Group, demonstrated a processor operating at fully 3.5 GHz.
But that's not the half of it. Otellini went on to note that the Pentium4 microarchitecture is expected to scale to a whopping 10 GHz.
Now that's a "Wow!"
But, exciting as speed is, it isn't everything. While it is important,"it is not sufficient to drive the levels of growth and innovation that will allow our industry to prosper," Otellini said.
Speaking before an audience of 4,000 developers, designers, and executives Tuesday, Otellini noted that as the computing industry has grown and new technologies have evolved, purchasing criteria are changing. "We all need to change the pattern of our investments," he cautioned the crowd. "We need to think beyond gigahertz and build substantially better computers."
Buyers now look to a variety of features, noted Otellini: style, form factor, security, power consumption, reliability, communications functions, price, and overall user experience. Combinations of these and other features are driving end-user technology requirements in individual market segments. Intel plans to develop technologies that will help address these changing requirements in each of the key market segments.
Here are just a few of the ways Intel plans to go beyond gigahertz, as Otellini revealed in his keynote address:
It's like multiple processors on a single chip
Otellini introduced the audience to a breakthrough in processor design called hyper-threading. This technology allows microprocessors to handle more information at the same time by sharing computing resources more efficiently. The technology provides a 30 percent performance boost in certain server and workstation applications and will first appear next year in the Intel® Xeon[tm] processor family.
This makes me wonder, how many Crusoe processors could you put in a box (all other components equal) and equal this power consumption? Would the performance of such a box meet or exceed the performance of an Itanium box for real-world servers?
For all intensive purposes, "whom" is no longer a word. That begs the question, "who cares"?
Someone needs to defend the SPARC chipset, and what [I see] Sun Microsystems is doing, so here I am.
Sure the single processor, or even up to 8 processor results are not the greatest thing out there. In the single through four processor units Intel beats them, and higher the Power series takes over. What one tends to forget is, for a processor that is designed for SMP, A) 1024 processors linearly is damn good, and B) it is relatively cheap for a server class processor. Also the SPARC line is known to have the least number of hardware bugs of any major processor out there.
Sun really doesn't need a sports car of a chip anyway. Servers and workstations need uptime. They don't need to attack the user market yet. First they seem to be more actively attacking the workstation market with the sub-$1000 SunBlades. With a Sun solution the workstation only needs to be moderately fast, but the server needs to be DAMN fast because the most intensive processes run on the server and display over the network. Small steps.
Disclamer - Opinion of Person