Gallium Arsenide Semiconductors on the Horizon

Masem writes: "According to this Chicago Tribune article, Motorola has developed a cheaper solution for putting gallium arsenide on top of silicon in order to allow for better chip designs with speeds nearly 40 times what silicon only chips would allow. While it was well known that gallium arsenide addition was favorable, it was also very expensive; Motorola's new process (covered by 200+ patents) should keep the chip prices low when these new designs are released in 2 years." The AP says they've applied for 270 patents.

Comments

Convex, anyone?

[Apotsy]

Gallium arsenide chips have been around for a long time, but as the article says, they are limited to niche applications due to cost. Still, there was one company which actually shipped a mainframe built on GaAs chips -- Convex. It's actually kind of hard to find info on them these days (they were swallowed up by HP in the mid 90s), but this EE Times article has a bit of info.

Re:Convex, anyone?

[morcheeba]

Ah! That explains it. I knew Seymour Cray was working on a GaAs computer -- he had renounced silicon and was assembling some of the world's best GaAs equipment. So, that was bought by Tera

Here's the interesting part of my post: Tera replaced the 24 GaAs chips for one CMOS chip. Here's their blurb from the website:

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Early MTA systems had been built using Gallium Arsenide (GaAs) technology for all logic design. Today, GaAs parts are predominantly used in cellular phones, not high performance computers. As a result of the semiconductor market's focus on CMOS technology for computer systems, there is little support for GaAs technology.

Cray's transition to using CMOS technology in the MTA will occur in stages.

In the first stage, a single CMOS MTA "Torrent" microprocessor replaces 24 GaAs ASICs that had represented 16 different ASIC designs. Torrent chips support up to 128 virtual processors, or threads, and will run at least as fast as today's MTA processors. A Torrent chip requires 50 watts of power compared with 1,000 watts for the GaAs design. The Torrent processor board requires 1,025 connections versus 14,400 connections on the GaAs board.
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Somewhere else on their page they say the system is "Water cooled at 4KW per processor". So, even with the reduced-power CMOS, they are putting out a lot of heat!

Re:"40 times faster"

[SysKoll]

Excellent point. The propagation delays are now about 50-70% of the clock cycle of a modern digital chip at the current speeds of several hundred MHz.

So any improvement of the semiconductor commutation speed is just a "nice to have" technology these days. Think of it. Assume that your chip spends 70% of its time waiting for signal propagation. Even if you suddenly get your transistors to switch instantly (that is, infinitely fast), you'll only increase the speed of a cycle by 100/70 = 1.43, or 43%. And then no more improvements.

That's why the biggest performance increases will now come from breakthrough in signal propagation speed: Copper wires, low-K dielectric, and more layers for denser circuits.

-- SysKoll

They're geniuses... maybe

[mbmclaur]

There's a similar article in EE times. www.eetimes.com/story/OEG20010904S0028) Sounds like they're using something called a "compliant substrate". The idea is that if the substrate is very thick relative to the film being grown then the tendency is for the film to deform it's lattice to match the substrate. The lattice strain stores energy, and as the film increases in thickness the amount of strain energy per unit volume of film increases. If the mismatch between substrate lattice dimensions and film dimensions is large enough the strain energy per unit volume can become large enough to nucleate dislocations at the interface. These dislocations allow the film to "relax" back to something near it's equilibrium lattice dimensions by periodically deleting or adding atomic planes near the interface. The problem is that these dislocations can thread up into the top of the film (i.e. where the device layers are) and act as non-radiative recombination centers and carrier traps. The dislocations can also jump from one layer to subsequently grown layers. A compliant substrate tries to force the substrate to deform, and thus the strain E in the film never gets high enough to nucleate dislocations. For example, if you make the substrate very thin then as the film grows the substrate will deform to match the equilibrium lattice dimensions of the film rahter than the other way round. Traditionally in Si technology this has been done by ion implanting O2 in a thin layer some small distance below the surface fo the wafer. The wafer is then annealed to let the crystal structure recover from all the damage the ions did to the surface. This leaves a thin layer of "single crystal" silicon floating on a thin layer of glass. At growth temperatures of >1000 C in MOCVD the glass layer is fairly gooey, and the thin silicon layer practically floats on it. So as long as the epi film is thicker than the Si compliant substrate you're golden. But this adds 2 steps to the production run, and ion implanting isn't generally a high throughput process. (i.e. $$$$$$$$$$$$$) Seems like Motorola's trick is to deposite a layer of some oxide with a crystal structure similar to GaAs. They then let oxygen diffuse down into the Si to form glass. So they bipass the implantation step. The intermediate layer probably doesn't match the GaAs exactly anyway, which means you still get dislocations. Alot fo Motorola's research time and patents were probably devoted to converting existing techniques for reducing dislocation density to work with the intermediate layer material. Anyway, I hope this gives you some idea of why I'm kinda skeptical. Old dog, maybe not-so-new tricks. But if Motorola has pulled it off it would be pretty sweet.

GaAs problems.. Si ain't so bad

[crgrace]

GaAs has been used for chips for years. Cost is of course a problem but there are others that make it very unlikely this will be used in general purpose microprocessors. The first problem is GaAs has a much higher defect density than silicon because it is a superlattice of gallium and arsenic and not a single crystal like silicon. For this reason GaAs chips have MUCH less yield than silicon chips so the number of transistors that can be integrated in GaAs in much less, even if it is put on a silicon substrate.

The second problem is the lack of a good thermal oxide in the GaAs material system. Silicon uses SiO2 which is an excellent insulator and more importantly has an extremely clean interface with silicon, so there are very few traps at the oxide-si interface. Because GaAs doesn't have a good oxide, MOS field-effect transistors (MOSFETS) are impossible and so digital GaAs chips use MESFETS, which are FETs without the oxide. It turns out the good oxide in silicon makes a lot of things possible that are impossible in GaAs. For example, the si oxide makes for a very high input impedance for Si transistors so they can be used to make dense RAM and very simple registers that rely on a high impedenence node. This structures are not possible in GaAs so more complicated, higher power circuits are required in GaAs to achieve the same functionality.