IBM Launches p690
edyavno writes: "IBM just announced the launch of their new high-end Unix server p690. It's based on its new Power 4 chip, and is in the same category as just announced Sun's SunFire 15K. It also includes some mainframe level features and can be used either as a single large server or divided into up to 16 "virtual" servers, running any combination of AIX 5L and Linux. Here's yahoo article, and here it is from IBM itself."
I grabbed this from IBM's website (http://www-1.ibm.com/servers/eserver/pseries/hard ware/datactr/p690.html):
- Innovative, mainframe-inspired, datacenter-class UNIX
server.
- 8- to 32-way 64 bit SMP server utilizing the first ever
POWER4 dual processor on a chip which uses IBM advanced
silicon-on-insulator (SOI) copper technology.
- Up to 256GB of memory, 160 PCI slots and over 4.6TB of
internal storage.
- Supports up to 16 logical partitions (LPAR), helping to
consolidate workloads, reduce footprints and lower cost of
ownership.
- A dedicated Hardware Management Console that provides a
graphical user interface for configuring and operating the
system including a set of functions for managing LPAR
configurations
- State-of-the-art self-managing capabilities that improve
reliability, availability and serviceability (RAS) and help lower
costs.
- Packaging in a new 24-inch rack with an integrated power
subsystem which accommodates a pSeries 690 system and up
to four I/O drawers.
- AIX clustering and future to attach to SP systems.
It looks very good. I just wonder what you would use 160 PCI slots for?
IBM's comparing their new server against the wrong Sun server. Here's why:
For unmatched UNIX system performance, the pSeries 690 can scale to a 32-way symmetric multiprocessor (SMP) helping to provide the scalability required to drive a UNIX datacenter.
A Sun Fire 15k contains up to 106 processors (72 with max i/o), a Sun Enterprise 10k contains up to 64 processors, and a Sun Fire 6800 contains 24 processors. Honestly this IBM server should be compared with either the 10k or 6800. It just can't scale as high as either the 10k or the 15k.
LPAR support for up to 16 UNIX or Linux partitions
Humm, first generation unix partitioning from IBM, or 5th generation partitioning from Sun (with help from Cray early on). BTW, a 10k can be in 16 partitions. No it doesn't require a domain to contain 4 processors--that's the max. A single board domain can have 1 i/o card, 1 cpu and some memory--typically a gig. The 15k and 6800 are similar, although the cpu/memory cards are typically maxed. It is *very* rare to find a company who would buy these sorts of systems to not max them out.
AIX 5L offers support for systems with up to 32 processors and 256 GB memory.
Wow, Solaris scales to 106 procesors in a single domain, with at least 1/2TB of memory. Besides, I'd bet there are more apps for Solaris than AIX.
*Note all of the quotes are from IBM's web page regarding the p690.
"If you insist on using Windoze you're on your own."
>absolutely nothing at all to do with the PPC
... apart from the fact that they share the same fucking instruction set, genius.
Overview of the Power4 processor:
Power4 is the processor that will be used in the next-generation RS/6000 and AS/400 systems (IBM eServer i-series and p-series). It is a high-performance VLSI chip that includes two 64-bit PowerPC microprocessors, connected at high bandwidth to an on-chip memory subsystem consisting of a shared L2-cache memory plus the directory and interface for a large off-chip L3, and with high-speed busses and I/O to enable efficient 8-way systems to be built on a single 4-chip module. The microprocessors will operate at > 1 GHz clock frequency and have processor-L2 cache bandwidths of 100 GB/s. The Power4 chip is divided into 12 units, some of which are being designed by multi-site teams. The Research team focuses on all aspects of VLSI design as well as design tools and methodologies. For the Instruction Fetch and L2 Cache Control Units, the circuit and physical design of the logic circuits (about 2M transistors for each unit) are done in Yorktown, the array designs in Poughkeepsie, and the logic and verification in Austin. Performance exceeding 1GHz is achieved at acceptable power levels using mostly static, custom-designed CMOS circuits for the dataflow. Synthesized logic, implemented using circuit books from a standard cell library, is used for most control circuits. The circuits are designed to be fabricated in IBM's 0.18 CMOS 8S2 Silicon-on-Insulator technology with 7 levels of copper wiring.
IBM would be very interested to hear that. You could save them a BUNDLE on all those PowerPC manuals....
POWER-1 was the blueprint for the original PowerPC 601. The 601 basically had the same instruction set, but a few instructions were removed (and handled in software). Some of the original Apple software was actually complied with xlC for the POWER instruction set (perf. wasn't great since a handful of instructions were trapped but it worked). IBM's POWER line of processors continued, but were modified to be PowerPC-compliant to the 64bit PPC spec.
Tom
If the past decade, and especially the past few years have thought us anything, it's that it is no longer about what feels right, if it ever was.
And any company but especially a tech company couldn't care less about your feelings of loyalty and 'right', or those of their empolyees, if it impacts their bottom line.
In the capitalist economy, the ever shrinking margins have long since squeezed conscience out of the corporate picture.