HP Shows Off PA-8800 SMP-On-A-Chip CPU Plans

Eric^2 writes: "At last week's MicroProcessor Forum, HP's David J. C. Johnson unveiled the details of HP's latest RISC processor destined to redefine performance in Server-Class processors. Following a relatively simple strategy, the PA-8800 processor combines two PA-8700 cores on a single chip to enable symmetric multiprocessing (SMP) on a single processor. Aside from bumping the core speed up to an initial 1 GHz, enhancements include the addition of combined 35 MB L1+L2 cache. The article contains the full text. AMD, please steal an idea..."

Comments

And Get Sued?

[tomblackwell]

These companies tend to patent anything that will give them a competitive edge in the marketplace. "Stealing an idea" would probably get them into some legal hot water, just like stealing a TV, or your car.

HP PA-8800 integer numbers

[Spootnik]

PA-8800 lets you create two opposite predicates in one instruction, for example the predicate a=b.

This seems to indicate that there are no separate "do this if predicate is true" and "do this if predicate is false" instructions, so for opposite predication you would have to specify two different predicates.

The processor cannot know that these two predicates are related, so this would give you quite a problem.

As has been publicly disclosed, in general in PA-8800, an instruction reading any resource (such as a predicate) must be in a later instruction group (cycle) than the instruction writing that resource. As a special case, branches are allowed to use a predicate written by another instruction in the same instruction group (as shown in the IDF slides).

So, the straightforward (but slow) PA-8800 schedule for the earlier example:

if (a < 0)
b += a;
else
b -= a;
c += b;
d += b;

would be:

cmp.lt pLT, pNLT = a, 0 // pLT & pNLT are 2 complementary preds
;;
(pLT) add b = b, a // add to b [then]
(pNLT) sub b = b, a // or sub from b [else]
;;
add c = c, b // uses of b
add d = d, b
;;

which takes 5 instructions in 3 cycles. (Note: In PA-8800 assembly, ";;" indicates the end of an instruction group, "=" separates the target operand(s) from the source(s), "//" begins a comment, and (pred) specifies the controlling predicate.)

An alternate (faster) schedule in PA-8800 is as follows:

sub bTmp = b, a // speculatively sub from b (into temp)
add b = b, a // and add to b
cmp.lt pLT, pNLT = a, 0
;;
(pLT) add c = c, b // uses of b [then]
(pLT) add d = d, b
(pNLT) add c = c, bTmp // uses of b (temp) [else]
(pNLT) add d = d, bTmp
(pNLT) mov b = bTmp // move bTmp to b [else]
;;

This takes 8 instructions in 2 cycles and one extra register. The final move of bTmp to b can be eliminated if b isn't live out at that point.