HP Shows Off PA-8800 SMP-On-A-Chip CPU Plans

Eric^2 writes: "At last week's MicroProcessor Forum, HP's David J. C. Johnson unveiled the details of HP's latest RISC processor destined to redefine performance in Server-Class processors. Following a relatively simple strategy, the PA-8800 processor combines two PA-8700 cores on a single chip to enable symmetric multiprocessing (SMP) on a single processor. Aside from bumping the core speed up to an initial 1 GHz, enhancements include the addition of combined 35 MB L1+L2 cache. The article contains the full text. AMD, please steal an idea..."

Comments

Two CPUs on a chip.

[Animats]

That makes sense. Two CPUs on a chip isn't a new idea, though. The IBM Power4 PowerPC chip is very similar, with two PowerPC processors on the same die. There's even a module with 4 such chips (8 processors) inside a machined aluminum block. That's intended as a building block for supercomputers.

Earlier steps in the multi-CPU direction included the 8-way DEC Alpha (killed in the merger with HP?) and a little National Semiconductor product for embedded systems with two very modest CPUs on a chip.

Re:just to make sure nobody is misled...

[svirre]

Risc or cisc architecture primarily affect the complexity of the fetch and decode stages of the CPU.

The famous Intel-pipeline is in the execute stage (ALU).

Pipelining is a strategy which is equally valid for both risc as in cisc architectures, and a risc architecture do not offer any complexity advantage in the execute stage. After all a multiplier is a multiplier regardless of overlaying architecture.

Nowdays we don't really see much diffrence in performance between risc and cisc architecures for upscale processors. This is because the savings in fetch and decode logic are dwarfed by other costs like prefetch, reordering and brach prediction (which are used for both architectures).