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OpenCores.org ARM Clone Removed From Web

Posted by timothy on from the mirror-mirror-on-the-net dept.

An Anonymous Coward writes: ""A clone of the ARM7 32-bit RISC processor core, previously available free for download from the Internet, has been taken down or hidden" pending discussions between the core's designer and a Chinese representative of ARM Holdings plc (Cambridge, England)." Remember, this is a reverse-engineered "clone in the form of a synthesizable Verilog language description."

2 of 124 comments (clear)

  1. Utterly ridiculous, and I've designed with an ARM7 by Anonymous Coward · · Score: 5, Insightful

    Having a synthesizable core does NOT mean that you can just drop it into any modern design. The deliverables for a commercially usable core are significant. Typically you need the following:

    * Verilog code.
    * TWO sets of timing constraints in Synopsys SDC format - one for synthesis, the other for static timing analysis and back-end physical design (i.e. defined clocks, high fanout nets like resets/selects, false/multicycle paths, case analysis statements for setting fastest propagation mode through the design).
    * Synthesis scripts, which have specific mappings to the standard-cell libraries of the particular process (except if implemented in an FPGA).
    * SRAM macro definitions and how they plug into the Verilog code (again, highly library/process specific and not relevant for an FPGA, assuming you can find enough on-board FPGA SRAM to equal the caches necessary for the ARM7)
    * All JTAG-related files, including BSDL and tap controller specs.
    * Scan and functional test vectors for Verilog VCS or NC-Verilog to show the core works.

    I'm sure I've missed a couple of things, but you get all of that, PLUS implementation support from ARM engineers. Mere Verilog code is not going to threaten ARM, and the expense that a company would go to in supporting its own core implementation wouldn't justify the cost in development time. Especially when there are other competitors ready to do it faster and quicker.

    So, IMO, I say SCREW ARM. Arrogant bastards who don't want people to learn about their own cores. Heck, big EDA companies give away their software to universities for education but that can't be used for commercial purposes (which was a big advantage in me getting a job in teh industry). Why can't ARM get their act together and do the same? It will only help to have engineers out of school who know their stuff.

  2. patented? by gmp · · Score: 5, Insightful

    The idea that a verilog description can infringe a patent is very problematic. Patents are supposed to teach an invention, but collect roalties on (or block) implementations. A verilog description is nothing more than a very detailed teaching of how to practice the art described in the patent. If the patent is valid (and you don't have any other objections to patent law in general) then there is no legal problem blocking someone from making a chip based on the verilog. But a patent holder has absolutely no right to block someone from teaching, in great detail, how to practice the art described in the patent (which after all was what the inventor was supposed to do when the patent was filed in the first place). Unless there is some trade secret misappropriation going on here, or unless ARM is claiming a copyright on their architecture that blocks any implementation of it, ARM appears to have no legal basis for what they are doing. As for the copyright theory, good luck getting that to stand in the US (see Lotus v. Borland).